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Taking acidified Cd contaminated brown soil in Yantai as the research object, based on different exogenous salinity (NaCl) gradient (0%, 0.3%, 0.6%, 0.9%, 1.5%, 2% and 5%), indoor simulation experiments of Cd release were carried out after field investigation. Results showed that there was a significantly positive relation (r>0.90) between Cd release concentration/amount/ratio and exogenous salt (NaCl). Besides, the more exogenous salt (NaCl) was added; maximum release concentration/amount of Cd appeared the earlier. It was found that exogenous salt (NaCl) addition could obviously promote Cd release from acidified Cd contaminated brown soil. It was believed that this could be mainly due to the cation exchange between Cd2+ and Na+, together with the dissociation and/or complexation between Cl- and Cd2+. In addition, available adsorption sites reduction by exchange base in soil causing Cd changed from solid state to soil solution was also a probable reason.

To improve the full well capacity (FWC) of a small size backside illuminated (BSI) CMOS image sensor (CIS), the effect of photodiode capacitance (CPD) on FWC is studied, and a reformed pinned photodiode (PPD) structure is proposed. Two procedures are implemented for the optimization. The first is to form a varying doping concentration and depth stretched new N region, which is implemented by an additional higher-energy and lower-dose N type implant beneath the original N region. The FWC of this structure is increased by extending the side wall junctions in the substrate. Secondly, in order to help the enlarged well capacity achieve full depletion, two step P-type implants with different implant energies are introduced to form a P-type insertion region in the interior of the stretched N region. This vertical inserted P region guarantees that the proposed new PD structure achieves full depletion in the reset period. The simulation results show that the FWC can be improved from 1289e− to 6390e−, and this improvement does not sacrifice any image lag performance. Additionally, quantum efficiency (QE) is enhanced in the full wavelength range, especially 6.3% at 520 nm wavelength. This technique can not only be used in such BSI structures, but also adopted in an FSI pixel with any photodiode-type readout scheme.

The charge transfer efficiency improvement method is introduced by optimizing the electrical potential distribution under the transfer gate along the charge transfer path. A non-uniform doped transfer transistor channel is introduced to provide an ascending electrical potential gradient in the transfer transistor channel. With the adjustments to the overlap length between the R1 region and the transfer gate, the doping dose of the R1 region, and the overlap length between the anti-punch-through (APT) implantations and transfer gate, the potential barrier and potential pocket in the connecting region of transfer transistor channel and the pinned photodiode (PPD) are reduced to improve the electrical potential connection. The simulation results show that the percentage of residual charges to total charges drops from 1/104 to 1/107, and the transfer time is reduced from 500 to 110 ns. This means the charge transfer efficiency is improved.