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The reliability of ultra-thin (1.38 nm–2.14 nm EOT) hafnium silicate gate dielectrics was studied to determine their suitability for incorporation into large-scale integration processes at sub-100 nm channel length. The reliability study includes a discussion of the evolution of current with time during a constant voltage stress, deduction of Weibull slopes, voltage acceleration and an estimate of the 10-year maximum operating voltage for devices fabricated with these layers. Finally, the change in Weibull slope at increased current step magnitude for constant voltage stress is used to observe the change in trap generation rate during a CVS until breakdown. [ABSTRACT FROM AUTHOR]

The temperature-dependent breakdown of silicon oxynitride gate dielectrics was studied to determine their reliability at and above operating temperatures. This paper demonstrates that the Weibull slopes of the ultra-thin layers are temperature dependent in the range from room temperature to 200 °C, and furthermore different behaviour is observed for pmos and nmos structures, with pmos structures not suffering any reliability loss at elevated temperature. We highlight that the improved reliability may simply be related to the problem of detecting the ‘real’ breakdown in the layers. Further to this we find an interesting effect where temperature and voltage can be used interchangeably to stress an oxide, and propose a method of normalizing stress data collected at a number of stress temperatures to one reference temperature. The findings support a voltage-dependent voltage acceleration. [ABSTRACT FROM AUTHOR]