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We propose a novel growth technique, in which graphene is synthesized on capped Cu thin films deposited on c-plane sapphire. The cap is another sapphire plate which is just laid upon the Cu thin film, in direct contact with it. Thanks to this 'contact cap', Cu evaporation can be suppressed at high temperature and the 400 nm-thick Cu films can be annealed above 1000 °C, resulting in (1 1 1)-oriented grains of millimeter size. Following this high temperature annealing, graphene is grown by chemical vapor deposition during the same pump-down operation, without removing the contact cap. The orientation and doping type of the as-grown graphene were first studied, using low energy electron diffraction, as well as high resolution angle-resolved photoemission spectroscopy. In particular, the orientation relationships between the graphene and copper thin film with respect to the sapphire substrate were precisely determined. We find that the graphene sheets exhibit a minimal rotational disorder, with ~90% of the grains aligned along the copper high symmetry direction. Detailed transport measurements were also performed using field-effect transistor structures. Carrier mobility values as high as 8460 cm2 V−1 s−1 have been measured on top gate transistors fabricated directly on the sapphire substrate, by etching the Cu film from underneath the graphene sheets. This is by far the best carrier mobility value obtained to date for graphene sheets synthesized on a thin film-type metal substrate.

The ability to grow carbon nanotubes/nanofibres (CNs) with a high degree of uniformity is desirable in many applications. In this paper, the structural uniformity of CNs produced by plasma enhanced chemical vapour deposition is evaluated for field emission applications. When single isolated CNs were deposited using this technology, the structures exhibited remarkable uniformity in terms of diameter and height (standard deviations were 4.1 and 6.3% respectively of the average diameter and height). The lithographic conditions to achieve a high yield of single CNs are also discussed. Using the height and diameter uniformity statistics, we show that it is indeed possible to accurately predict the average field enhancement factor and the distribution of enhancement factors of the structures, which was confirmed by electrical emission measurements on individual CNs in an array.

We report on the fabrication of field emission microcathodes which use carbon nanotubes as the field emission source. The devices incorporated an integrated gate electrode in order to achieve truly low-voltage field emission. A single-mask, self-aligned technique was used to pattern the gate, insulator and catalyst for nanotube growth. Vertically-aligned carbon nanotubes were then grown inside the gated structure by plasma-enhanced chemical vapour deposition. Our self-aligned fabrication process ensured that the nanotubes were always centred with respect to the gate apertures (2 µm diameter) over the entire device. In order to obtain reproducible emission characteristics and to avoid degradation of the device, it was necessary to operate the gate in a pulsed voltage mode with a low duty cycle. The field emission device exhibited an initial turn-on voltage of 9 V. After the first measurements, the turn-on voltage shifted to 15 V, and a peak current density of 0.6 mA cm-2 at 40 V was achieved, using a duty cycle of 0.5%.

We present a systematic study of grain size and carrier mobility behaviour in polycrystalline graphene films grown on copper substrates with various surface roughness values. We first observe that as the surface roughness of the substrate decreases, the graphene grain size increases significantly, thus decreasing the density of grain boundaries. Then, using field-effect transistor structures, we confirm that as the substrate roughness decreases, carrier mobility values in graphene increase, whatever the channel length of the transistor. For a substrate rms roughness around 5 nm (measured on a 10 × 10 µm2 field) and using a fast growth process (~40 min), we obtain mobility values as high as ~6900 cm2 Vs−1 for electrons and ~6000 cm2 Vs−1 for holes in polycrystalline graphene with a small grain size of ~12–14 µm.

Silicon nanowires have been synhesized using Al as a catalyst. Silane (SiH4) diluted in H2 carrier gas was employed as Si precursor in a plasma enhanced chemical vapor deposition system operated at various temperatures (450 °C and 550 °C). Those growth temperatures, which are lower than the eutectic temperature in the Al–Si system (577 °C) suggests a vapor–solid–solid growth mechanism. Four point resistance measurements and back-gated current-voltage measurements indicated that silicon nanowires were heavily doped (p type), with a doping concentration of a few 1019 cm−3. We have measured hole mobility values of ~16 cm2 V−1 s−1 at 450 °C and ~30 cm2 V−1 s−1 at 550 °C. Transmission electron microscope analyses showed that the silicon nanowires were highly twinned even when they grow epitaxially on (111) Si substrates. We have also evaluated the use of those highly doped Si nanowires for lithium-ion battery anodes. We have observed a good cycling behavior during the first 65 charge–discharge cycles, followed by a slow capacity decay. After 150 cycles at a charge–discharge rate of 0.1 C, the electrode capacity was still 1400 mAh g−1. The ageing mechanism seems to be related to the delamination of the SiNWs from the stainless steel substrate on which they were grown.

In this paper, we briefly review the use of carbon nanotubes and semiconductor nanowires, which represent a new class of nanomaterials actively studied for thin film transistors and electronics applications. Although these nanomaterials are usually synthesised at moderate to high temperatures, they can be transferred to any kind of substrate after growth, paving the way for the fabrication of flexible displays and large area electronics systems on plastic. Over the past few years, the field has progressed well beyond the realisation of elementary devices, since active matrix displays driven by nanowire thin film transistors have been demonstrated, as well as the fabrication of medium scale integrated circuits based on random arrays of carbon nanotubes. Also, graphene, a new nanomaterial has appeared in the landscape; although it is a zero gap semiconductor, it can still be used to make transistors, provided narrow ribbons or bilayers are used. Graphene is also a serious contender for the replacement of oxide-based transparent conducting films.

Doping control on carbon nanotubes (CNTs) is a crucial step for implementation in future nanodevices. Chemical doping of CNTs is typically done via functionalization. Controlling the dopant types and position on the CNT-based thinfilm transistors (TFTs) and their stability has been a considerable challenge. Here, we report a CNT doping strategy utilizing ionic adsorbates controlled via gate and drain bias. Dopant type was controlled by the polarity of the gate bias, and positioning of the adsorbates was expedited by applying drain and gate bias. This enabled us to control n- or p-type doping that leads to drain-to-source or source-to-drain direction of Schottky diodes. The combined adsorbate-associated biasing method also allowed a selective dissociation

Interface state creation, induced by hot hole injection, has been frequently observed in n-channel polysilicon thin-film transistors, when subjected to prolonged bias stress with negative gate biases. In this work we propose a new model for the kinetics of interface state formation, that closely links the interface state generation to the measured gate leakage current. The interface state generation mechanism appears to be driven by the recombination of hot holes (injected from the semiconductor active layer) with electrons (injected from the gate electrode). This model is shown to fit very well the time evolution of the interface states, as determined by the sheet conductance of the damaged region close to the drain.

The kinetics of crystallization of high-purity amorphous and mixed-phase silicon films obtained by pyrolysis of disilane gas in the millitorr pressure range were studied. A combination of in situ electrical conductance measurements and transmission electron microscopy analysis was used to determine the crystallization parameters. For mixed-phase films we report an activation energy for the nucleation rate of the order of 2.9 eV, compared to approximately 3.7 eV for the completely amorphous ones; the activation energy for the growth rate is roughly equal to 2.7 eV for the two types of films analyzed.

The deposition of high electrical quality SiO2 films on Si wafers has been achieved without substrate heating, (T2/SiH4) on the dielectric behavior of DECR SiO2. The electrical performances of both Si-SiO2 interfaces and SiO2 films in metal-oxide-semiconductor (MOS) structures were assessed by several characterization methods including critical field (E c) evaluation, fixed charge densities (Q ox) and interface traps densities (D it) determinations. We report typical values of E c around 6 MV·cm-1, and Q ox and D it densities around 2×1010 cm-2 and 3×1010 cm-2·eV-1 respectively. Thin film SOI-MOSFETs have also been fabricated to prove the DECR oxide quality.