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A low power 10-bit 250 MSPS charge-domain (CD) pipelined analog-to-digital converter (ADC) is introduced. The ADC is implemented in MOS bucket-brigade devices (BBDs) based CD pipelined architecture. A replica controlled boosted charge transfer (BCT) circuit is introduced to reject the influence of PVT variations on the charge transfer process. Based on replica controlled BCT, the CD pipelined ADC is designed and realized in a 1P6M 0.18 μ m CMOS process. The ADC achieves the SFDR of 64.4 dB, the SNDR of 56.9 dBFS and the ENOB of 9.2 for a 9.9 MHz input; and the SFDR of 63.1 dB, the SNR of 55.2 dBFS, the SNDR of 54.5 dBFS and the ENOB of 8.7 for a 220.5 MHz input at full sampling rate. The DNL is +0.5/-0.55 LSB and INL is +0.8/-0.85 LSB. The power consumption of the prototype ADC is only 45 mW at 1.8 V supply and it occupies an active die area of 1.56 mm2.