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The paper reports high-performance enhancement-mode MOS high-electron mobility transistors (MOS-HEMTs) based on a quaternary InAlGaN barrier. Self-aligned gate technology is used for gate recessing, dielectric deposition, and gate electrode formation. An improved digital recessing process is developed, and an Al2O3 gate dielectric grown with O2 plasma is used. Compared to results with AlGaN barrier, the fabricated E-mode MOS-HEMT with InAlGaN barrier delivers a record output current density of 1.7 A/mm with a threshold voltage (V TH) of 1.5 V, and a small on-resistance (R on) of 2.0 Ω·mm. Excellent V TH hysteresis and greatly improved gate leakage characteristics are also demonstrated.

Self-aligned-gate heterostructure field-effect transistor (HFET) is fabricated using a wet-etching method. Titanium nitride (TiN) is one kind of thermal stable material which can be used as the gate electrode. A Ti/Au cap layer is fixed on the gate and acts as an etching mask. Then the T-shaped gate is automatically formed through over-etching the TiN layer in 30% H2O2 solution at 95 °C. After treating the ohmic region with an inductively coupled plasma (ICP) method, an Al layer is sputtered as an ohmic electrode. The ohmic contact resistance is approximately 0.3 Ωmm after annealing at a low-temperature of 575 °C in N2 ambient for 1 min. The TiN gate leakage current is only 10−8 A after the low-temperature ohmic process. The access region length of the self-aligned-gate (SAG) HFET was reduced from 2 μm to 0.3 μm compared with that of the gate-first HFET. The output current density and transconductance of the device which has the same gate length and width are also increased.

We report a new approach in fabricating a self-aligned gate GaN MOSFET. The fabrication technique is based on a double-layer photoresist (PR) and low-temperature-Ohmic formation process assisted by an inductively coupled plasma (ICP) dry etching process. In this process, the active region was automatically defined by the combination of a subsequently developed positive PR and the existing negative PR pattern. The Al Ohmic electrodes on the ICP-treated active region were formed by a lift-off process followed by 500 °C N2 1 min annealing. The specific contact resistance of 4.8 × 10−6 Ω cm2 was obtained in this process. Operation up to a gate bias of 30 V was confirmed. The maximum output current of 98 mA mm−1 and field-effect mobility of 110 cm2 V−1 s−1 were observed in the device with a gate length of 4 μm. Some non-ideal effects in this device, including the negative threshold voltage, larger off-state leakage and unsaturated on-state drain current, were also observed and analyzed. Some possible ways to improve the performance of the device were proposed.

Field-effect transistors (FETs) are fabricated using an optimized gate-all-around gate-overlap structure and an InAs/InP core–shell nanowire (NW) channel. A short-channel device with the gate length of 100 nm exhibits superb on-state properties. Subthreshold swing of 85 mV/decade is realized in a long-channel device, suggesting an advantage of the core–shell NW channel. Post-annealing is found to improve the subthreshold properties, which is partly ascribed to the formation of InAlAs alloy at the interface between the InAs core and Al source/drain electrodes.

Self-aligned-gate Pt/SrBi2Ta2O9/HfAlO/Si metal/ferroelectric/insulator/semiconductor (MFIS) field-effect transistors (FETs) were fabricated. Drain current (I d) versus gate voltage curves of the MFIS FETs showed almost the same steepness as that of a non-self-aligned-gate Pt/HfAlO/Si metal/insulator/semiconductor FET. Long retention times with large on- and off-state I d ratios were obtained for the MFIS FETs. The retention times more than 33 days with an on- and off-state I d ratio over 105 were demonstrated for the self-aligned-gate MFIS FET with a 2-µm-long and 80-µm-wide gate. This device showed the longest memory retention among all of the ferroelectric-gate FETs reported ever before.

We studied electroluminescence (EL) intensity distributions in the direction of gate width of n+ self-aligned gate GaAs metal-semiconductor field-effect transistors (MESFETs). Nonuniform EL was observed along the gate-width direction, suggesting the nonuniform high-field formation in the direction of the gate. It has also been found that the EL at the source side shows gentler distribution than that at the drain side. These features suggest that the nonuniform hole distribution generated by impact ionization at the drain side becomes gradual during the process of their flow into the source and gate electrodes.

In this paper we report on a self-aligned gate buried-channel Al0.22Ga0.78As/GaAs heterostructure field-effect transistor (BC-HFET). The BC-HFET comprises a selectively ion-implanted channel and an undoped i-AlGaAs surface layer. In order to realize the buried channel heterostructure, a combined process of ion-implantation and epitaxial growth is developed. The post-implantation annealing before the epitaxial growth successfully reduces the interdiffusion at the heterointerface between the ion-implanted GaAs channel and the AlGaAs surface layer. The BC-HFET overcomes the disadvantages of a low breakdown voltage which exists in conventional self-aligned gate MESFETs. The BC-HFET exhibits a high breakdown voltage of 8 V and a high Schottky barrier height of 0.75 eV. The 1-mm-wide power BC-HFET demonstrates an output power of 18.2 dBm and a drain efficiency of 50% at a low adjacent channel leakage power of -59 dBc for a 1.9-GHz π/4-shifted quadrature phase shift keying (QPSK) modulated input, for use as Personal Handy-phone System handsets.

We studied the electroluminescence (EL) for n+self-aligned gate GaAs metal-semiconductor field-effect transistors (MESFETs) at room temperature. It has been found that the spatial distribution of the EL intensity is dependent on the luminescence energy. The EL peak with bandgap energy is observed at a region between the source and the gate metals, while the EL with an energy higher than the band gap energy is observed on the drain-side edge of the gate. By studying the correlation between the integrated EL intensity and the drain/gate current, it is concluded that the electron-hole recombination is a dominant luminescence mechanism for both the high and low energy regions for the present n+self-aligned gate GaAs MESFETs.

We have developed a refractory WN x /W self-aligned gate GaAs power metal-semiconductor field-effect transistor (MESFET) for use in L-band digital mobile communication systems. This power MESFET operates with high efficiency and low distortion at a gate bias of 0 V and a low drain bias of 2.7 V, because of its small drain knee voltage, high transconductance and sufficient breakdown voltage. This power MESFET is quite promising for a highly efficient linear power amplifier IC operating with a single low-voltage supply. Good output characteristics of the power MESFET with 1 mm gate width were attained for π/4-shifted quadrature phase shift keying (QPSK) modulated input signals in the 1.9-GHz band, such as an output power of 18.4 dBm, a power gain of 19.0 dB and a high power-added efficiency of 26.4% when a sufficiently low adjacent channel leakage power of -58 dBc was obtained.

It was found that lanthanum hexaboride (LaB6) forms a thermally stable Schottky contact with a high barrier height of about 0.9 V on a chemically-etched n-type GaAs(100) substrate. GaAs metal-semiconductor field effect transistors (MESFET's) having excellent DC characteristics were obtained using LaB6 as a self-aligned gate. The high barrier height enabled normally-off MESFFT's to have a large operation margin.