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Integration of high-k/metal gate stacks in peripheral transistors is a major candidate to ensure continued scaling of dynamic random access memory (DRAM) technology. In this paper, the CMOS integration of diffusion and gate replacement (D&GR) high-k/metal gate stacks is investigated, evaluating four different approaches for the critical patterning step of removing the N-type field effect transistor (NFET) effective work function (eWF) shifter stack from the P-type field effect transistor (PFET) area. The effect of plasma exposure during the patterning step is investigated in detail and found to have a strong impact on threshold voltage tunability. A CMOS integration scheme based on an experimental wet-compatible photoresist is developed and the fulfillment of the main device metrics [equivalent oxide thickness (EOT), eWF, gate leakage current density, on/off currents, short channel control] is demonstrated.

PAC measurements on show that the U moments are oriented mainly along [001] in an AFII type ordering. A small scale deviation from this ordering must be present, for which two possibilities are proposed. There are several indications that on top of this small scale deviation another not yet understood perturbative effect occurs.

We report on the temperature dependence of the 111Cd magnetic hyperfine field in bcc-Co as measured in Fe/Co multilayers. An anomalous increase of the hyperfine field with temperature is observed. Below the growth temperature of the samples, the behaviour can be explained by simple thermal expansion of the lattice. At 570 K a relaxation of the interplanar distance accounts for the anomaly. This relaxation is interpreted as an onset to the degeneration of the forced bcc structure to an energetically more favorable Co-phase.

This paper discusses integration aspects of a porous low-k film (k ∼2.45) cured with a broadband UV lamp. Different process splits are discussed which could contribute to avoid integration induced damage and improve reliability. The main factor contributing to a successful integration is the presence of a thick (protecting) cap layer partially remaining after chemical mechanical polishing (CMP), which leads to yielding structures with a k eff of ∼2.6, a breakdown voltage of ∼6.9 MV/cm and time dependent dielectric breakdown (TDDB) lifetimes in the excess of 100 years. Long thermal anneals restore the k-value but degrade lifetime.

Aurora® LK HM (k=3.2) material has been successfully integrated into 30 nm half pitch structures. This material outperforms Aurora® LK (k=3.0) in terms of breakdown field strength and mechanical properties. Scaling of the physical vapor deposition (PVD) based barrier/seed process and adjusting of the barrier chemical mechanical polishing (CMP) overpolish condition were yield enabling factors. No degradation of the breakdown field upon reducing half pitch is observed down to 30 nm for line lengths up to at least 1 mm. The median time-dependent dielectric breakdown (TDDB) lifetime, as evaluated on a 1 mm 35 nm half pitch parallel line structure, exceeds 10 years at an electrical field of 2.6 MV/cm.