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Recognition of the potentially massive computational power of a quantum computer has driven a considerable experimental effort to build such a device. Of the various possible physical implementations, silicon-based architectures are attractive for the long spin relaxation times involved, their scalability, and ease of integration with existing silicon technology. However, their fabrication requires construction at the atomic scale-an immense technological challenge. Here we outline a detailed strategy for the construction of a phosphorus in silicon quantum computer and demonstrate the first significant step towards this goal-the fabrication of atomically precise arrays of single phosphorus bearing molecules on a silicon surface. After using a monolayer hydrogen resist to passivate a silicon surface we apply pulsed voltages to a scanning tunnelling microscope tip to selectively desorb individual hydrogen atoms with atomic resolution. Exposure of this surface to the phosphorus precursor phosphine results in precise placement of single phosphorus atoms on the surface. We also describe preliminary studies into a process to incorporate these surface phosphorus atoms into the silicon crystal at the array sites.

We use controlled annealing to tune the interfacial properties of a sub-monolayer and monolayer coverages of Ba atoms deposited on Ge(001), enabling the generation of either of two fundamentally distinct interfacial phases, as revealed by scanning tunneling microscopy. Firstly we identify the two key structural phases associated with this adsorption system, namely on-top adsorption and surface alloy formation, by performing a deposition and annealing experiment at a coverage low enough (∼0.15 ML) such that isolated Ba-related features can be individually resolved. Subsequently we investigate the monolayer coverage case, of interest for passivation schemes of future Ge based devices, for which we find that thermal evaporation of Ba onto a Ge (001) surface at room temperature results in on-top adsorption. This separation (lack of intermixing) between Ba and Ge layers is retained through successive annealing steps to temperatures of 470, 570, 670 and 770 K although a gradual ordering of the Ba layer is observed at 570 K and above, accompanied by a decrease in Ba layer density. Annealing above 770 K produces the 2D surface alloy phase accompanied by strain relief through monolayer height trench formation. An annealing temperature of 1070 K sees a further change in surface morphology but retention of the 2D surface alloy characteristic. These results are discussed in view of their possible implications for future semiconductor integrated circuit technology.