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Nanoscale vacuum channel transistors (NVCTs) have garnered considerable interest due to their outstanding high frequency characteristics and high reliability, stemming from a distinct carrier transport mechanism compared to solid-state devices. Electrons traverse the nanoscale vacuum channel through scattering-free ballistic transport. However, existing research has predominantly focused on the structural design and optimization of NVCTs, with relatively few studies delving into their high frequency performance. Hence, alongside structural exploration and optimizing, investigating the high-frequency characteristics of NVCTs assumes particular importance. In this study, a novel NVCTs with a gate-cathode height difference structure was proposed and its electrical characteristics were simulated. Simulation results reveal that the presence of gate-cathode height difference effectively enhance the DC characteristics of NVCTs. Moreover, high frequency simulation demonstrate that the proposed device can operate frequency exceeding 1 THz. Whitin the GHz and even terahertz (THz) range, NVCTs exhibits exceptional high frequency properties, including ultrafast response times and minimal distortion. These findings not only offer insights for future structural design and optimization of NVCTs but also underscore the potential of NVCTs in radio frequency and THz applications. [ABSTRACT FROM AUTHOR]

Optoelectronic synapses are inevitable for realizing neuromorphic vision systems, which require the integration of image recognition, memory and image processing into a single platform. In this work, we present a three terminal optoelectronic synapse created using zinc oxide (ZnO) thin film transistor. The persistent photoconductivity (PPC) of ZnO thin film is utilized to demonstrate the synaptic behavior. The change in conductance of the device under UV illumination has been interpreted as the weight change in the synapse. The basic synaptic functions such as sensory memory, short term memory, long term memory, duration-time-dependent plasticity and paired pulse facilitation (PPF) have been successfully demonstrated. The device shows a PPF index of 160%, comparable to other optoelectronic synapses reported in literature. Further, to corroborate the existing theory that PPC is caused by oxygen vacancies, additional characterizations are carried out and the presence of oxygen vacancies is detected in the fabricated ZnO device. Subsequently, pattern recognition of MNIST handwritten dataset has been performed using the conductance tuning curves of the proposed ZnO TFT based synapses in a neural network architecture, thereby demonstrating their feasibility to be used in neuromorphic applications. [ABSTRACT FROM AUTHOR]

Sn-doped indium oxide (ITO) semiconductor nano-films are fabricated by plasma-enhanced atomic layer deposition using trimethylindium (TMIn), tetrakis(dimethylamino)tin (TDMASn), and O2 plasma as the sources of In, Sn and O, respectively. A shared temperature window of 150 °C– 200 °C is observed for the deposition of ITO nano-films. The introduction of Sn into indium oxide is found to increase the concentration of oxygen into the ITO films and inhibit crystallization. Furthermore, two oxidation states are observed for In and Sn, respectively. With the increment of interfaces of In–O/Sn–O in the ITO films, the relative percentage of In3+ ions increases and that of Sn4+ decreases, which is generated by interfacial competing reactions. By optimizing the channel component, the In0.77Sn0.23O1.11 thin-film transistors (TFTs) demonstrate high performance, including μ FE of 52.7 cm2 V−1 s−1, and a high I ON/ I OFF of ∼5 × 109. Moreover, the devices show excellent positive bias temperature stress stability at 3 MV cm−1 and 85 °C, i.e. a minimal V th shift of 0.017 V after 4 ks stress. This work highlights the successful application of ITO semiconductor nano-films by ALD for TFTs. [ABSTRACT FROM AUTHOR]

Molybdenum disulfide (MoS2) is a representative two-dimensional layered transition-metal dichalcogenide semiconductor. Layer-number-dependent electronic properties are attractive in the development of nanomaterial-based electronics for a wide range of applications including sensors, switches, and amplifiers. MoS2 field-effect transistors (FETs) have been studied as promising future nanoelectronic devices with desirable features of atomic-level thickness and high electrical properties. When a naturally n -doped MoS2 is contacted with metals, a strong Fermi-level pinning effect adjusts a Schottky barrier and influences its electronic characteristics significantly. In this study, we investigate multilayer MoS2 Schottky barrier FETs (SBFETs), emphasizing the metal-contact impact on device performance via computational device modeling. We find that p -type MoS2 SBFETs may be built with appropriate metals and gate voltage control. Furthermore, we propose ambipolar multilayer MoS2 SBFETs with asymmetric metal electrodes, which exhibit gate-voltage dependent ambipolar transport behavior through optimizing metal contacts in MoS2 device. Introducing a dual-split gate geometry, the MoS2 SBFETs can further operate in four distinct configurations: p − p, n − n, p − n, and n − p. Electrical characteristics are calculated, and improved performance of a high rectification ratio can be feasible as an attractive feature for efficient electrical and photonic devices. [ABSTRACT FROM AUTHOR]

The spin field effect transistor (sFET), proposed by Datta and Das (1990 Appl. Phys. Lett. 56 665–7), has long been regarded as a model semiconductor spintronic device, offering potential for new, more energy-efficient functionalities in electronic devices. Here, the overview is given how the pursuit of meeting the requirements for implementing the sFET concept has influenced spintronic research, leading to a greater understanding of spin phenomena in solids and resulting in numerous exciting effects. After looking back, based on the recent developments, the possible future directions of the sFET-related research are described. [ABSTRACT FROM AUTHOR]

A normally-off vertical gallium nitride (GaN) junction field-effect transistor (JFET) is demonstrated in this work. The device shows an on/off current ratio of 3.6 × 1010, a threshold voltage (V TH) of 1.64 V, and a specific on-resistance (R ON,SP) of 1.87 mΩ·cm2. Drain-induced channel effects were proposed to explain the change in the gate current at different drain voltages. Drain current decline in the output characteristics and the reverse turn-on between drain and source can be explained by effects. A technological computer-aided design was used to simulate the change of the depletion region and confirm the explanation. Detailed analyses of the channel effects provide a reference for the design of novel structures. The characteristics at different temperatures demonstrated the stability of threshold voltage and specific on-resistance, thus indicating the great potential of applications in switching power circuits of vertical GaN JFETs. [ABSTRACT FROM AUTHOR]

Opto-neuromorphic operation is critical for biological system to recognize the visual objects and mimicking such operation is important for artificial prosthesis as well as machine vision system for industrial applications. To sophisticatedly mimic biological system, regulation of learning and memorizing efficiency is needed, however engineered synthetic platform has been lack of controllability, which makes huge gap between biological system and synthetic platform. Here we demonstrated controllable learning and memorizing opto-neuromorphic operation at plasmonic hot electron transistor. Especially, circularly polarized light (CPL) sensitive synaptic characteristics and learning experience capability are enabled by incorporating chiral plasmonic nanoparticle. Furthermore, gate voltage gives rise to controllable neuromorphic operation due to hot electron injection and trapping effect, resulting in high remaining synaptic weight of ∼70% at negative gate voltage under CPL excitation. We believe that this discovery makes significant leap toward on-demand in-sensor computing as well as toward bio-realistic device. [ABSTRACT FROM AUTHOR]

The field-effect transistor (FET) is a fundamental component of semiconductors and the electronic industry. High on-current and mobility with layer-dependent features are required for outstanding FET channel material. Two-dimensional materials are advantageous over bulk materials owing to their higher mobility, high ON/OFF ratio, low tunneling current, and leakage problems. Moreover, two-dimensional heterostructures provide a better way to tune electrical properties. In this work, the two distinct possibilities of PdSe2/MoSe2 heterostructure have been employed through mechanical exfoliation and analyzed their electrical response. These diffe approaches to heterostructure formation serve as crucial components of our investigation, allowing us to explore and evaluate the unique electronic properties arising from each design. This work demonstrates that the heterostructure possesses a better ON/OFF ratio of ∼5.78 × 105, essential in switching characteristics. Moreover, MoSe2 provides a defect-free interface to PdSe2, resulting in a higher ON current of ∼10 μ A and mobility of ∼63.7 cm2V−1s−1, necessary for transistor applications. In addition, comprehending the process of charge transfer occurring at the interface between transition metal dichalcogenides is fundamental for advancing next-generation technologies. This work provides insights into the interface formed between the PdSe2 and MoSe2 that can be harnessed in transistor applications. [ABSTRACT FROM AUTHOR]

Low-voltage operation is one of the prerequisites for the practical applications of the organic thin-film transistors (OTFTs). Up to date, the most reported low-voltage operatable OTFTs use a bottom-gate structure, and are fabricated by several different technologies in the whole process, in which the organic semiconductors and/or gate dielectrics are prepared in the expensive vacuum equipment. The simple fabricating technologies and fewer processes can better demonstrate the inherent advantages, and enhance the commercial competitiveness of OTFTs. Here, we propose a strategy to fabricate the binary polymers gate dielectric by one-step spin-coating in the top-gate structured flexible OTFTs, by which not only the device performances are prominently improved, but also the fabricating process of the OTFTs is minimized. As a result, the flexible OTFTs exhibit a high mobility over 0.5 cm2 Vs−1, low threshold voltage near to −0.5 V, and excellent mechanical bending durability with a very slightly performances degradation after the tensile and compressive bending at a small curvature radius of 3.0 mm over 1000 cycles. [ABSTRACT FROM AUTHOR]

In this paper, we demonstrate experimentally that field-effect transistors with nanoconstricted graphene monolayer channels have a subthreshold swing (SS) below 60 mV/dec, which is slightly dependent on temperature. Two shapes of nanoconstricted graphene monolayers are considered: (i) a bow-tie shape, representative for a symmetric channel, and (ii) a trapezoidal shape, which illustrates an asymmetric channel. While both types of nonuniform channels are opening a bandgap in graphene, thus showing an on/off ratio of 105, the SS in the graphene bow-tie channel is below 60 mV/dec in the temperature range 25 °C–44 °C. [ABSTRACT FROM AUTHOR]

To enable the application to next-generation devices of semiconductor nanowires (NWs), it is important to control their formation and tune their functionality by doping and the use of heterojunctions. In this paper, we introduce formation and the characterization methods of nanowires, focusing on our research results. We describe a top-down method of controlling the size and alignment of nanowires that shows advantages over bottom-up growth methods. The latter technique causes damage to the nanowire surfaces, requiring defect removal after the NW formation process. We show various methods of evaluating the bonding state and electrical activity of impurities in NWs. If an impurity is doped in a NW, mobility decreases due to the scattering that it causes. As a strategy for solving this problem, we describe research into core–shell nanowires, in which Si and Ge heterojunctions are formed in the diameter direction inside the NW. This structure can separate the impurity-doped region from the carrier transport region, promising as a channel for the new ultimate high-mobility transistor. [ABSTRACT FROM AUTHOR]

We demonstrate an InGaZnO (IGZO)-based synaptic transistor with a TiO2 buffer layer. The structure of the synaptic transistor with TiO2 inserted between the Ti metal electrode and an IGZO semiconductor channel O2 trapping layer produces a large hysteresis window, which is crucial for achieving synaptic functionality. The Ti/TiO2/IGZO synaptic transistor exhibits reliable synaptic plasticity features such as excitatory post-synaptic current, paired-pulse facilitation, and potentiation and depression, originating from the reversible charge trapping and detrapping in the TiO2 layer. Finally, the pattern recognition accuracy of Modified National Institute of Standards and Technology handwritten digit images was modeled using CrossSim simulation software. The simulation results present a high image recognition accuracy of ∼89%. Therefore, this simple approach using an oxide buffer layer can aid the implementation of high-performance synaptic devices for neuromorphic computing systems. [ABSTRACT FROM AUTHOR]

The 2T1C pixel driver circuit for mini-LED direct display has been proposed, which separates the switching transistor and the driver transistor from the same display substrate, replaces the driver transistor with n-metal oxide semiconductor (NMOS), and combines printed circuit board substrate and thin-film transistor (TFT) substrate to improve the driving capability of the circuit. The NMOS was soldered with mini-LEDs simultaneously onto a substrate which connects to the a-Si TFT array. Two driving modes for a 32-level gray-scale display panel were investigated to compare the voltage-current and optical characteristics. The results demonstrated that the drain-driving mode is better suited for high brightness and high-power display application scenarios as it supports higher-driven currents, but the source-driving mode is more appropriate for precision gray-scale applications due to the higher current linearity of the mode. [ABSTRACT FROM AUTHOR]

The use of electrolyte-gated transistors (EGTs) as sensors can be an advantageous alternative for the detection of anionic molecules due to their capability to detect various ions in solution. In this study, we explore the potential of EGTs as analytical tools for detecting anionic molecules, utilizing a copper phthalocyanine-3,4′,4″,4‴-tetrasulfonic acid tetrasodium salt (CuTsPc) solution as a proof of concept. The results demonstrate the EGT's capacity in detecting CuTsPc in an aqueous solution, which molecule dissociates into sodium ions (Na+) and CuPc(SO3−)4 ions, leading to high ionic conductivity and the formation of electrical double layers (EDLs). Varying the concentration of the molecule induced alterations in the EDLs, exhibiting good linearity and sensitivity in the transconductance, and a detection limit of 6.0 × 10−8 mol l−1. Transistors employing the CuTsPc solution as electrolyte operated at low voltages and performed better than water-gated transistors (W-GTs). The transconductance (gm) value for EGTs using CuTsPc solution reached 1.93 mS, while for W-GTs it was around 0.10 mS. Thus, the CuTsPc solution not only serves as a target-molecule in sensor measurements, but also demonstrates potential as an electrolyte in EGTs, thereby assuming a dual role within the device. The main advantage of the EGTs as an analytical tool is their use as a multiparameter device that enables the detection of the analytes using different phenomena that occur at the EDLs interface and which, consequently, changes the device's performance. [ABSTRACT FROM AUTHOR]

Two-dimensional transition metal dichalcogenides (TMDs), as flexible and stretchable materials, have attracted considerable attention in the field of novel flexible electronics due to their excellent mechanical, optical, and electronic properties. Among the various TMD materials, atomically thin MoS2 has become the most widely used material due to its advantageous properties, such as its adjustable bandgap, excellent performance, and ease of preparation. In this work, we demonstrated the practicality of a stacked wafer-scale two-layer MoS2 film obtained by transferring multiple single-layer films grown using chemical vapor deposition. The MoS2 field-effect transistor cell had a top-gated device structure with a (PI) film as the substrate, which exhibited a high on/off ratio (108), large average mobility (∼8.56 cm2 V−1 s−1), and exceptional uniformity. Furthermore, a range of flexible integrated logic devices, including inverters, NOR gates, and NAND gates, were successfully implemented via traditional lithography. These results highlight the immense potential of TMD materials, particularly MoS2, in enabling advanced flexible electronic and optoelectronic devices, which pave the way for transformative applications in future-generation electronics. [ABSTRACT FROM AUTHOR]

Two-dimensional (2D) van der Waals (vdW) p-type semiconductors have shown attractive application prospects as atomically thin channels in electronic devices. However, the high Schottky hole barrier of p-type semiconductor–metal contacts induced by Fermi-level pinning is hardly removed. Herein, we prepare a vdW 1T-CoS2 nanosheet as the contact electrode of a WSe2 field-effect transistor (FET), which shows a considerably high on/off ratio > 107 and a hole mobility of ∼114.5 cm2 V−1 s−1. The CoS2 nanosheets exhibit metallic conductivity with thickness dependence, which surpasses most 2D transition metal dichalcogenide metals or semimetals. The excellent FET performance of the CoS2-contacted WSe2 FET device can be attributed to the high work function of CoS2, which lowers the Schottky hole barrier. Our work provides an effective method for growing vdW CoS2 and opens up more possibilities for the application of 2D p-type semiconductors in electronic devices. [ABSTRACT FROM AUTHOR]

The layer-by-layer (LbL) technique has been proven to be one of the most versatile approaches in order to fabricate functional nanofilms. The use of simple and inexpensive procedures as well as the possibility to incorporate a very wide range of materials through different interactions have driven its application in a wide range of fields. On the other hand, field-effect transistors (FETs) are certainly among the most important elements in electronics. The ability to modulate the flowing current between a source and a drain electrode via the voltage applied to the gate electrode endow these devices to switch or amplify electronic signals, being vital in all of our everyday electronic devices. In this topical review, we highlight different research efforts to engineer field-effect transistors using the LbL assembly approach. We firstly discuss on the engineering of the channel material of transistors via the LbL technique. Next, the deposition of dielectric materials through this approach is reviewed, allowing the development of high-performance electronic components. Finally, the application of the LbL approach to fabricate FETs-based biosensing devices is also discussed, as well as the improvement of the transistor's interfacial sensitivity by the engineering of the semiconductor with polyelectrolyte multilayers. [ABSTRACT FROM AUTHOR]

Reservoir computing has been considered as a promising intelligent computing paradigm for effectively processing complex temporal information. Exploiting tunable and reproducible dynamics in the single electronic device have been desired to implement the "reservoir" and the "readout" layer of reservoir computing system. Two-dimensional moiré materials, with an artificial lattice constant many times larger than the atomic length scale, are one type of most studied artificial quantum materials in community of material science and condensed-matter physics over the past years. These materials are featured with gate-tunable periodic potential and electronic correlation, thus varying the electric field allows the electrons in the moiré potential per unit cell to exhibit distinct and reproducible dynamics, showing great promise in robust reservoir computing. Here, we report that a moiré synaptic transistor can be used to implement the reservoir computing system with a homogeneous reservoir-readout architecture. The synaptic transistor is fabricated based on an h-BN/bilayer graphene/h-BN moiré heterostructure, exhibiting ferroelectricity-like hysteretic gate voltage dependence of resistance. Varying the magnitude of the gate voltage enables the moiré transistor to switch between long-term memory and short-term memory with nonlinear dynamics. By employing the short- and long-term memories as the reservoir nodes and weights of the readout layer, respectively, we construct a full-moiré physical neural network and demonstrate that the classification accuracy of 90.8% can be achieved for the MNIST (Modified National Institute of Standards and Technology) handwritten digits database. Our work would pave the way towards the development of neuromorphic computing based on moiré materials. [ABSTRACT FROM AUTHOR]

The trench diamond junction barrier Schottky (JBS) diode with a sidewall enhanced structure is designed by Silvaco simulation. Comparing with the conventional trench JBS diode, Schottky contact areas are introduced on the sidewall of the trench beside the top cathode. The sidewall Schottky contact weakens the junction field-effect transistor effect between the trenches to realize a low on-resistance and a high Baliga's figure of merit (FOM) value. In addition, the existence of the n-type diamond helps to suppress the electric field crowding effect and enhance the reverse breakdown voltage. With the optimal parameters of device structure, a high Baliga's FOM value of 2.28 GW/cm2 is designed. Therefore, the proposed sidewall-enhanced trench JBS diode is a promising component for the applications in diamond power electronics. [ABSTRACT FROM AUTHOR]

We fabricate top-gate transistors on the three-layer molybdenum disulfide (MoS2) with three, two, and one layers in the source and drain regions using atomic layer etching (ALE). In the presence of ALE, the device at zero gate voltage can exhibit high and low levels of drain current under the forward and reverse gate bias, respectively. The hysteresis loop on the transfer curve of transistor indicates that two distinct charge states exist in the device within a range of gate bias. A long retention time of the charge is observed. Unlike conventional semiconductor memories with transistors and capacitors, the two-dimensional (2D) material itself plays two parts in the current conduction and charge storage. The persistent charge storage and memory operation of the multilayer MoS2 transistors with thicknesses of a few atomic layer will further expand the device application of 2D materials with reduced linewidths. [ABSTRACT FROM AUTHOR]

Ferroelectric transistors hold great potential in low consumption devices. Due to the high film quality and clean system, two dimensional organic semiconductors are widely employed to fabricate high performance organic electronic devices and explore the modulation mechanism of the molecular packing on device performance. Here, we combine the ferroelectric hafnium oxide HfZrO x and two-dimensional molecular crystal 2,9-didecyldinaphtho[2,3-b:2′,3′-f]thieno[3,2b]thiophene (C10-DNTT) with controllable layers to study the molecular layer modulation of ferroelectric organic thin-film transistors (OTFTs). The contact resistance, driving current and transconductance are directly affected by the additional access resistance across the upper molecular layers at the source/drain contact region. Simultaneously, the capacitance of Schottky junction related to the molecular layer thickness could effectively adjust the gate potential acting on the organic channel, further controlling the devices' subthreshold swing and transconductance efficiency. This work would promote the development of low voltage and high performance OTFTs. [ABSTRACT FROM AUTHOR]

To strengthen the downscaling potential of top-gate amorphous oxide semiconductor (AOS) thin-film transistors (TFTs), the ultra-thin gate insulator (GI) was comparatively implemented using the atomic-layer-deposited (ALD) AlO x and HfO x. Both kinds of high- k GIs exhibit good insulating properties even with the physical thickness thinning to 4 nm. Compared to the amorphous indium-gallium-zinc oxide (a-IGZO) TFTs with 4 nm AlO x GI, the 4 nm HfO x enables a larger GI capacitance, while the HfO x -gated TFT suffers higher gate leakage current and poorer subthreshold slope, respectively originating from the inherently small band offset and the highly defective interface between a-IGZO and HfO x. Such imperfect a-IGZO/HfO x interface further causes noticeable positive bias stress instability. Both ALD AlO x and HfO x were found to react with the underneath a-IGZO channel to generate the interface defects, such as metal interstitials and oxygen vacancies, while the ALD process of HfO x gives rise to a more severe reduction of a-IGZO. Moreover, when such a defective interface is covered by the top gate, it cannot be readily restored using the conventional oxidizing post-treatments and thus desires the reduction-resistant pre-treatments of AOSs. [ABSTRACT FROM AUTHOR]

The voyage of semiconductor industry to decrease the size of transistors to achieve superior device performance seems to near its physical dimensional limitations. The quest is on to explore emerging material systems that offer dimensional scaling to match the silicon- based technologies. The discovery of atomic flat two-dimensional materials has opened up a completely new avenue to fabricate transistors at sub-10 nanometer level which has the potential to compete with modern silicon-based semiconductor devices. Molybdenum disulfide (MoS2) is a two-dimensional layered material with novel semiconducting properties at atomic level seems like a promising candidate that can possibly meet the expectation of Moore's law. This review discusses the various ' fabrication challenges ' in making MoS2 based electronic devices from start to finish. The review outlines the intricate challenges of substrate selection and various synthesis methods of mono layer and few-layer MoS2. The review focuses on the various techniques and methods to minimize interface defect density at substrate/MoS2 interface for optimum MoS2-based device performance. The tunable band-gap of MoS2 with varying thickness presents a unique opportunity for contact engineering to mitigate the contact resistance issue using different elemental metals. In this work, we present a comprehensive overview of different types of contact materials with myriad geometries that show a profound impact on device performance. The choice of different insulating/dielectric gate oxides on MoS2 in co-planar and vertical geometry is critically reviewed and the physical feasibility of the same is discussed. The experimental constraints of different encapsulation techniques on MoS2 and its effect on structural and electronic properties are extensively discussed. [ABSTRACT FROM AUTHOR]

This paper reports the influence of an ultrathin 1.5 nm atomic-layer-deposited HfO2 blanket layer as a gate dielectric on GaN high-electron-mobility transistors (HEMTs) grown on a 4H-SiC substrate. Transistors with a gate length of 250 nm and a source-to-drain distance of 3 µ m were manufactured. The proposed technique involves HfO2 deposition at 250 ∘C prior to the gate metallization with no additional lithography steps. This approach reduced the drain lag by 83% compared to the conventional design with no gate dielectric. The HfO2 layer suppressed the parasitic lateral conduction from the gate, reduced surface trapping, and improved gate electrostatics. The manufactured devices exhibited nearly three orders of magnitude decreased surface leakage, better turn-on behavior, and improved cut-off frequency f T linearity by 16%. High quality metal-oxide interface formation was confirmed by the conductance method. Results demonstrate that the blanket HfO2 deposition is a promising approach to improve the current dispersion characteristics and gate electrostatics of GaN HEMTs without incurring major changes to the established fabrication techniques. [ABSTRACT FROM AUTHOR]

The synaptic devices based on various electronic materials have been widely investigated to realize functions of artificial information processing with low power consumption. In this work, a novel CVD graphene field-effect transistor is fabricated with ionic liquid gate to study the synaptic behaviors based on the electrical-double-layer mechanism. It is found that the excitative current is enhanced with the pulse width, voltage amplitude and frequency. With different situations of the applied pulse voltage, the inhibitory and excitatory behaviors are successfully simulated, at the same time the short-term memory is also realized. The corresponding ions migration and charge density variation are analyzed in the different time segments. This work provides the guidance for the design of artificial synaptic electronics with ionic liquid gate for low-power computing application. [ABSTRACT FROM AUTHOR]

As down scaling of transistors continues, there is a growing interest in developing steep-slope transistors with reduced subthreshold slope (SS) below the Boltzmann limit. In this work, we successfully fabricated steep-slope MoS2 transistors by incorporating a graphene layer, inserted in the gate stack. For our comprehensive study, we have applied density functional theory to simulate and calculate the change of SS effected by different 2D quantum materials, including graphene, germanene and 2D topological insulators, inserted within the gate dielectric. This theoretical study showed that graphene/MoS2 devices had steep SS (27.2 mV/decade), validating our experimental approach (49.2 mV/decade). Furthermore, the simulations demonstrated very steep SS (8.6 mV/decade) in WTe2/MoS2 devices. We conclude that appropriate combination of various 2D quantum materials for the gate-channel stacks, leads to steep SS and is an effective method to extend the scaling of transistors with exceptional performance. [ABSTRACT FROM AUTHOR]

A new stable current-sourcing transistor is developed using the band-to-band tunneling phenomenon. A heterojunction between thin film WS2 and heavily hole-doped bulk silicon converts a section of the WS2 contacting the silicon into a hole-doped WS2 inside the WS2 channel, and band-to-band tunneling occurs between the electron-doped and hole-doped WS2. The output current is regulated by the tunneling barrier thickness. The thickness depends on the gate bias for device switching, but is less sensitive to the source bias, enabling stable output currents. The minimum line sensitivity is 2.6%, and the temperature coefficient is 1.4 × 103 ppm ° Câˆ'1. The device can be operated as a current sourcing device with an ultralow output current and power consumption. [ABSTRACT FROM AUTHOR]

In this study, the homojunction thin-film transistors (TFTs) with amorphous indium gallium zinc oxide (a-IGZO) as active channel layers and source/drain electrodes were fabricated by RF magnetron sputtering. The effect of oxygen partial pressure on the phase, microstructure, optical and electrical properties of IGZO thin films was investigated. The results showed that amorphous IGZO thin films always exhibit a high transmittance above 90% and wide band gaps of around 3.9 eV. The resistivity increases as the IGZO thin films are deposited at a higher oxygen partial pressure due to the depletion of oxygen vacancies. In addition, the electrical behaviors in homojunction IGZO TFTs were analyzed. When the active channel layers were deposited with an oxygen partial pressure of 1.96%, the homojunction IGZO TFTs exhibited optimal transfer and output characteristics with a field-effect mobility of 13.68 cm2 Vâˆ'1 sâˆ'1. Its sub-threshold swing, threshold voltage and on/off ratio are 0.6 V/decade, 0.61 V and 107, respectively. [ABSTRACT FROM AUTHOR]

The negative gate bias stress (NBS) reliability of n-type polycrystalline silicon (poly-Si) thin-film transistors (TFTs) with a distinct defective grain boundary (GB) in the channel is investigated. Results show that conventional NBS degradation with negative shift of the transfer curves is absent. The on-state current is decreased, but the subthreshold characteristics are not affected. The gate bias dependence of the drain leakage current at V ds of 5.0 V is suppressed, whereas the drain leakage current at V ds of 0.1 V exhibits obvious gate bias dependence. As confirmed via TCAD simulation, the corresponding mechanisms are proposed to be trap state generation in the GB region, positive-charge local formation in the gate oxide near the source and drain, and trap state introduction in the gate oxide. [ABSTRACT FROM AUTHOR]

In this paper, an ultrascaled ballistic graphene nanoribbon field-effect transistor (GNRFET) endowed with a compound double-gate based on metal-ferroelectric-metal (MFM) structure is proposed to overcome the limitations encountered with its conventional counterpart. The ballistic transistor is computationally investigated by solving self-consistently the non-equilibrium Green’s function formalism and the Poisson solver in conjunction with the Landauâ€"Khalatnikov equation. The numerical investigation has included the ferroelectric-induced amplified internal metal voltage, the role of the ferroelectric thickness in boosting the device performance, the assessment of the switching and subthreshold performance, and the analysis of the FE-GNRFET scaling capability. The simulations revealed that the MFM-based gate can significantly boost the performance of GNRFETs, including the switching behavior, the on-current, the off-current, the current ratio, the swing factor, the intrinsic delay, and the scaling capability. More importantly, the proposed MFM GNRFET was found able to provide sub-thermionic subthreshold swing even with sub-10 nm gate lengths, which is very promising for low-power applications. The obtained results indicate that the MFM-based gating approach can give new impulses to the GNRFET technology. [ABSTRACT FROM AUTHOR]

We investigated the improvement methods of the electrical characteristics and reliability of flexible low-temperature polycrystalline silicon (LTPS) thin-film transistors (TFTs) by optimizing the annealing process. We investigated the effect of annealing on the device properties via electrical measurement and density-of-state (DOS) analysis. The annealing temperature should be reduced for flexible LTPS TFTs compared to rigid devices because the range of the thermal stability of flexible substrate is narrower than that of the glass substrate. As the activation annealing temperature (T a) decreased, the threshold voltage and field-effect mobility (ÎĽ FE) decreased, and the subthreshold swing (SS) increased. When the post-annealing temperature (T pa) decreased, ÎĽ FE increased, and the changes in the other parameters were negligible. The DOS decreased with an increase in T a and a reduction in T pa. These results originated from ineffective dopant activation and defect curing due to the lower T a and the enhanced hydrogen defect passivation at the lower T pa. Therefore, flexible LTPS TFTs with reduced T a values exhibited similar ÎĽ FE values and lower SS values when the post-annealing process was omitted. Furthermore, removing the post-annealing process improved the reliability of the flexible LTPS TFTs with reduced T a values under electrical stress. According to a hot-carrier instability analysis, defect passivation by hydrogen was more stable than defect curing with a higher T a. Consequently, although T a was low for flexible LTPS TFTs, the electrical performance and reliability could be improved by optimizing the post-annealing process. [ABSTRACT FROM AUTHOR]

We present a comprehensive numerical analysis of contact resistance in coplanar organic thin-film transistors. A large number of hole-transporting organic transistors are investigated through two-dimensional finite-element simulation, by deliberately changing the channel length, source/drain electrode thickness, and hole-injection energy barrier heights. Gate-field-dependent terminal contact resistances of these devices are fully estimated and electrostatic distributions inside the organic semiconductor film are visualized for the understanding of physical mechanisms. It is found that the relationship between source/drain electrode thickness and contact resistance does not follow any simple trend and is also strongly associated with the injection energy barrier. Moreover, the origin of negative contact resistance in organic transistors featuring a minimal charge-injection barrier is elaborated. Finally, a direct impact of the semiconductor charge-carrier mobility on contact resistance is addressed, revealing a linear dependence of contact resistance on inverse mobility over a broad parameter range. [ABSTRACT FROM AUTHOR]

In this paper, we present for the first time a field-effect-transistor (FET) having a 10 nm thick tin sulfide (SnS) channel fabricated at the wafer scale with high reproducibility. SnS-based FETs are in on-state for increasing positive back-gate voltages up to 6 V, whereas the off-state is attained for negative back-gate voltages not exceeding âˆ'6 V, the on/off ratio being in the range 102â€"103 depending on FET dimensions. The SnS FETs show a subthreshold slope (SS) below 60 mV/decade thanks to the in-plane ferroelectricity of SnS and attaining a minimum value SS = 21 mV/decade. Moreover, the low SS values can be explained by the existence of a negative value of the capacitance of the SnS thin film up to 10 GHz (for any DC bias voltage between 1 and 5 V), with the minimum value being âˆ'12.87 pF at 0.1 GHz. [ABSTRACT FROM AUTHOR]

Monolayer- and a few layers-black phosphorus (BP) is an emerging two-dimensional material for the post-silicon era. We study the transport mechanism and performance metrics of double-walled BP n-channel and p-channel gate-all-around nanotube (NT) transistors using a k â‹... p Hamiltonian and a non-equilibrium Green’s function quantum simulation. We effectively use the anisotropic effective masses along the zigzag and armchair directions of BP for high performance NT field-effect transistors. The heavy mass along the zigzag direction is used for quantization to increase the carrier density, while the lighter mass along the armchair direction is used for transport to maximize the carrier injection velocity. The on-state current is governed by the thermionic transport mechanism over the top of the potential barrier, while the off-state current is predominantly governed by intra-band tunneling current. Although the lighter mass in transport direction initiates intra-band tunneling current, the device can be successfully turned on and off with a high on/off current ratio of 1.4 Ă— 10 5 . The n-channel transistor has an on-state current of 724 µ A  µ mâˆ'1, a subthreshold slope of 63 mV decâˆ'1, a transconductance of 7.97 mS  µ mâˆ'1, a switching delay time of 3.92 ps, a cut-off frequency of 0.201 THz, and a dynamic power loss of 0.64 fJ  µ mâˆ'1, respectively. The corresponding performance metrics for the p-channel are 726 µ A  µ mâˆ'1, 64 mV decâˆ'1, 8.20 mS  µ mâˆ'1, 3.96 ps, 0.205 THz, and 0.65 fJ  µ mâˆ'1. Both the transistors are potential candidates for the International Technology Roadmap for Semiconductors 2026 low operating power devices. [ABSTRACT FROM AUTHOR]

We investigate the angular dependence of proton-induced single event transient (SET) in silicon-germanium heterojunction bipolar transistors. Experimental results show that the overall SET cross section is almost independent of proton incident angle. However, the proportion of SET events with long duration and high integral charge collection grows significantly with the increasing angle. Monte Carlo simulations demonstrate that the integral cross section of proton incident events with high ionizing energy deposition in the sensitive volume tends to be higher at larger incident angles, which is associated with the angular distribution of proton-induced secondary particles and the geometry of sensitive volume. [ABSTRACT FROM AUTHOR]

High throughput, high sensitivity, and scalability point-of-care biosensors have the potential to significantly improve diagnosis and disease monitoring. Organic electrochemical transistors (OECTs) are a powerful platform for point-of-care biosensing given their sensitivity and performance. Unfortunately, this is seldom achieved with novel and cost-effective fabrication methods. In this work, we built high-performance OECTs using state-of-the-art inkjet printing technology a, scalable, highly reproducible, and low-cost fabrication process. The design utilizes unique high conductivity PEDOT: PSS formulations driving higher ion-to-electron conversion, and volumetric capacitance reaching a value of 18.524 F cm−3 . The design included a high ratio of channel crosssectional area to length reaching a maximum corresponding transconductance (gm) value of 15.2 mS, an order of magnitude improvement on published work. The design was also tested with Bovine Serum Albumin (BSA) protein and showed a limit of detection on the order of 1 pM of BSA. This work shows the potential of inkjet printing for fabricating low-cost, high-performance OECT-based point-of-care biosensors. [ABSTRACT FROM AUTHOR]

MoS2 crystals grown by chemical vapor deposition are suited for realization of practical 2D semiconductor-based electronics. In order to construct complementary circuits with n-type MoS2, another p-type semiconductor, whose performance can be adjusted corresponding to that of MoS2 in the limited chip area, has to be sought. Herein, we present a method for tuning switching threshold voltages of complementary inverters simply via inkjet printing without changing their channel dimensions. Random networks of inkjet printed single-walled carbon nanotubes are formed as p-channels beside MoS2, and their density and thickness are controlled by varying the number of printed layers. As a result, p-type transistor characteristics as well as inverter characteristics are facilely tuned only by varying the number of printed layers. [ABSTRACT FROM AUTHOR]

The human brain that relies on neural networks communicated by spikes is featured with ultralow energy consumption, which is more robust and adaptive than any digital system. Inspired by the spiking framework of the brain, spike-based neuromorphic systems have recently inspired intensive attention. Therefore, neuromorphic devices with spike-based synaptic functions are considered as the first step toward this aim. Photoelectric neuromorphic devices are promising candidates for spike-based synaptic devices with low latency, broad bandwidth, and superior parallelism. Here, the indium-gallium-zinc-oxide-based photoelectric neuromorphic transistors are fabricated for Morse coding based on spike processing, 405-nm light spikes are used as synaptic inputs, and some essential synaptic plasticity, including excitatory postsynaptic current, short-term plasticity, and high-pass filtering, can be mimicked. More interestingly, Morse codes encoded by light spikes are decoded using our devices and translated into amplitudes. Furthermore, such devices are compatible with standard integrated processes suitable for large-scale integrated neuromorphic systems. [ABSTRACT FROM AUTHOR]

The reliable conductance modulation of synaptic devices is key when implementing high-performance neuromorphic systems. Herein, we propose a floating gate indium gallium zinc oxide (IGZO) synaptic device with an aluminum trapping layer to investigate the correlation between its diverse electrical parameters and pattern recognition accuracy. Basic synaptic properties such as excitatory postsynaptic current, paired pulse facilitation, long/short term memory, and long-term potentiation/depression are demonstrated in the IGZO synaptic transistor. The effects of pulse tuning conditions associated with the pulse voltage magnitude, interval, duration, and cycling number of the applied pulses on the conductance update are systematically investigated. It is discovered that both the nonlinearity of the conductance update and cycle-to-cycle variation should be critically considered using an artificial neural network simulator to ensure the high pattern recognition accuracy of Modified National Institute of Standards and Technology (MNIST) handwritten digit images. The highest recognition rate of the MNIST handwritten dataset is 94.06% for the most optimized pulse condition. Finally, a systematic study regarding the synaptic parameters must be performed to optimize the developed synapse device. [ABSTRACT FROM AUTHOR]

Atomically two-dimensional (2D) materials have generated widespread interest for novel electronics and optoelectronics. Specially, owing to atomically thin 2D structure, the electronic bandgap of 2D semiconductors can be engineered by manipulating the surrounding dielectric environment. In this work, we develop an effective and controllable approach to manipulate dielectric properties of h-BN through gallium ions (Ga+) implantation for the first time. And the maximum surface potential difference between the intrinsic h-BN (h-BN) and the Ga+ implanted h-BN (Ga+-h-BN) is up to 1.3 V, which is characterized by Kelvin probe force microscopy. More importantly, the MoTe2 transistor stacked on Ga+-h-BN exhibits p-type dominated transfer characteristic, while the MoTe2 transistor stacked on the intrinsic h-BN behaves as n-type, which enable to construct MoTe2 heterojunction through dielectric engineering of h-BN. The dielectric engineering also provides good spatial selectivity and allows to build MoTe2 heterojunction based on a single MoTe2 flake. The developed MoTe2 heterojunction shows stable anti-ambipolar behaviour. Furthermore, we preliminarily implemented a ternary inverter based on anti-ambipolar MoTe2 heterojunction. Ga+ implantation assisted dielectric engineering provides an effective and generic approach to modulate electric bandgap for a wide variety of 2D materials. And the implementation of ternary inverter based on anti-ambipolar transistor could lead to new energy-efficient logical circuit and system designs in semiconductors. [ABSTRACT FROM AUTHOR]

A negative capacitance transistor with fully depleted silicon-on-insulator (FDSOI) technology (NC-FDSOI) is one of the promising candidates for next-generation low-power devices. However, it suffers from the inherent negative differential resistance (NDR) effect, which is very detrimental to device and circuit designs. Aiming at overcoming this shortcoming, this paper proposes for the first time to use local Gaussian heavy doping technology (LoGHeD) in the channel near the drain side to suppress the NDR effect in the NC-FDSOI. The technical computer-aided design simulation results have validated that the output conductance (G DS) with LoGHeD, which is used to measure the NDR effect, increases compared to the conventional NC-FDSOI counterpart and approaches zero. With the increase in doping concentration, the inhibitory capability of the NDR effect shows a monotonously increasing trend. In addition, the proposed approach maintains and even enhances performances of the NC-FDSOI transistor regarding the electrical parameters, such as threshold voltage (V TH), sub-threshold swing, switching current ratio (I ON/ I OFF), and drain-induced barrier lowering. [ABSTRACT FROM AUTHOR]

When designing the gate-dielectric of a floating-gate-transistor, one must make a tradeoff between the necessity of providing an ultra-small leakage current behavior for long state retention, and a moderate to high tunneling-rate for fast programming speed. Here we report on a memristively programmable transistor that overcomes this tradeoff. The operation principle is comparable to floating-gate-transistors, but the advantage of the analyzed concept is that ions instead of electrons are used for programming. Since the mass of ions is significantly larger than the effective mass of electrons, gate-dielectrics with higher leakage current levels can be used. We demonstrate the practical feasibility of the device using a proof-of-concept study based on a micrometer-sized thin-film transistor and LT-Spice simulations of 32 nm transistors. Memristively programmable transistors have the potential of high programming endurance and retention times, fast programming speeds, and high scalability. [ABSTRACT FROM AUTHOR]

Recently, antimony-doped tin oxide nanoparticles (ATO NPs) have been widely used in the fields of electronics, photonics, photovoltaics, sensing, and other fields because of their good conductivity, easy synthesis, excellent chemical stability, high mechanical strength, good dispersion and low cost. Herein, for the first time, a novel nonvolatile transistor memory device is fabricated using ATO NPs as charge trapping sites to enhance the memory performance. The resulting organic nano-floating gate memory (NFGM) device exhibits outstanding memory properties, including tremendous memory window (∼85 V), superhigh memory on/off ratio (∼109), long data retention (over 10 years) and eminent multilevel storage behavior, which are among the optimal performances in NFGM devices based on organic field effect transistors. Additionally, the device displays photoinduced-reset characteristic with low energy consumption erasing operation. This study provides novel avenues for the manufacture of simple and low-cost data storage devices with outstanding memory performance, multilevel storage behavior and suitability as platforms for integrated circuits. [ABSTRACT FROM AUTHOR]

Three-dimensional (3D) vertical architecture transistors represent an important technological pursuit, which have distinct advantages in device integration density, operation speed, and power consumption. However, the fabrication processes of such 3D devices are complex, especially in the interconnection of electrodes. In this paper, we present a novel method which combines suspended electrodes and focused ion beam (FIB) technology to greatly simplify the electrodes interconnection in 3D devices. Based on this method, we fabricate 3D vertical core-double shell structure transistors with ZnO channel and Al2O3 gate-oxide both grown by atomic layer deposition. Suspended top electrodes of vertical architecture could be directly connected to planar electrodes by FIB deposited Pt nanowires, which avoid cumbersome steps in the traditional 3D structure fabrication technology. Both single pillar and arrays devices show well behaved transfer characteristics with an I on/ I off current ratio greater than 106 and a low threshold voltage around 0 V. The ON-current of the 2 Ă— 2 pillars vertical channel transistor was 1.2 ÎĽA at the gate voltage of 3 V and drain voltage of 2 V, which can be also improved by increasing the number of pillars. Our method for fabricating vertical architecture transistors can be promising for device applications with high integration density and low power consumption. [ABSTRACT FROM AUTHOR]

Two-dimensional (2D) molybdenum disulfide (MoS2) field-effect transistor (FET) gated by negative capacitance (NC) is a promising architecture to overcome the thermionic limit and thus reduce device consumption. Here, top-gated MoS2 NCFETs have been prepared by transferring a mica flake on MoS2 channel to form a van der Waals heterojunction interface, together with a ferroelectric HfZrO2 (HZO) deposited on mica. Stable NC effects are demonstrated for MoS2 NCFETs. The MoS2 NCFETs integrated with mica/HZO gate stack provide competitive electrical characteristics when they are applied with a gate voltage sweep-width in the range of 1−3 V and a sweep-rate from 0.01 to 0.2 V s−1, including steep-slope of sub 60 mV dec−1 in four orders of magnitude of drain current, on/off current ratio over 106, and small hysteresis-width less than 50 mV. Outstanding performance should be ascribed to damage-free properties of mica/MoS2 van der Waals interface and capacitance matching between the HZO ferroelectric and mica dielectric. The results confirm the promising nature of mica/HZO gate stack and potential applications for future electronics. [ABSTRACT FROM AUTHOR]

Recently, ferroelectric polarization coupling has been exploited for non-volatile p- and n-type doping of two-dimensional (2D) materials, which enables the design of 2D functional devices via a local polarization pattern. Here, we took advantage of this tool and study the effect of base width to the gain and photodetection performance of bipolar transistors made of few layer MoS2. We found that the space charge region in the base have typical width ∼150–250 nm, and depends on the applied external bias. Such a characteristic causes the compromise between transistor gain and shunt resistance when changing the base width. For photodetection, this hinders the optimization of responsivity without increasing the dark current. As a result, an optimal device was made at the base width ∼1040 nm, from which a responsivity of 160 A W−1, specific detectivity of ∼1.3 × 1012 and the response time ∼9 μs to 680 nm incident light was obtained. The results from the present study shed light on the further design of 2D functional devices that use lateral pn junctions as the basic building blocks. [ABSTRACT FROM AUTHOR]

Taking heat positively as the information carrier, thermotronics can exempt the long-lasting thermal issue of electronics fundamentally, yet has been faced with the challenging multiplexing integration of diverse functionalities. Here, we demonstrate a spatiotemporal modulation platform to achieve multiplexing thermotronics functionalities based on the thermal-hysteresis vanadium dioxide, including negative-differential thermal emission, thermal diode, thermal memristor, thermal transistor, and beyond. The physics behind the multiplexing thermotronics lies in the thermal hysteresis emission characteristics of the phase-changing vanadium dioxide during the spatiotemporal modulation. The present spatiotemporal modulation is expected to stimulate more exploration on novel functionalities, system integration, and practical applications of thermotronics. [ABSTRACT FROM AUTHOR]

We preform a first-principles study of performance of 5 nm double-gated (DG) Schottky-barrier field effect transistors (SBFETs) based on two-dimensional SiC with monolayer or bilayer metallic 1T-phase MoS2 contacts. Because of the wide bandgap of SiC, the corresponding DG SBFETs can weaken the short channel effect. The calculated transfer characteristics also meet the standard of the high performance transistor summarized by international technology road-map for semiconductors. Moreover, the bilayer metallic 1T-phase MoS2 contacts in three stacking structures all can further raise the ON-state currents of DG SiC SBFETs in varying degrees. The above results are helpful and instructive for design of short channel transistors in the future. [ABSTRACT FROM AUTHOR]

The MoS2 negative-capacitance field-effect transistor (NCFET) with the ultra-thin (3 nm) HfZrO (HZO) as NC layer and 2 nm Al2O3 as dielectric layer is successfully fabricated by optimizing the annealing temperature and the HZO thickness. Excellent subthreshold swing (SS = 33.1 mV dec−1) is achieved, with an on/off current ratio of 1.16 × 107. The relevant negative-drain-induced barrier lowing effect and the negative differential resistance effect are observed in the MoS2 NCFET. Such low SS implies that only a small gate-voltage increment can transfer the transistor from off state to on state, i.e. an excellent switching and low power-consumption characteristics. The involved mechanisms lie in a suitable anneal temperature for ferroelectric phase transition and a reasonably ultra-thin HZO thickness for the optimum capacitance matching. [ABSTRACT FROM AUTHOR]