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To avoid surface damage of a MoS2 channel, a mica flake with high permittivity and atomically flat surface was dry transferred onto a multilayer MoS2 flake to prepare top-gated transistors. For the first time, the interface properties of mica/MoS2 and the long-term stability of devices were investigated when the transistors were exposed to ambient air. Results show that the electrical performance of the transistors is degraded significantly when the devices are exposed to ambient moisture for a long time, due to the strong hydrophilism of mica. The transfer curves of the transistors cannot be recovered to their initial states even after annealing. The adsorbed moisture can become trapped at the interface between the MoS2 channel and mica dielectric or on the MoS2 surface, resulting in enhanced carrier scattering and degraded device performance. However, the top-gated MoS2 transistor with Al2O3 encapsulation exhibits enhanced stability even after annealing or exposure to atmosphere for 200 days. The excellent stability should be attributed to the effective insulation of moisture from the ambient air by Al2O3 encapsulation. Therefore, a dense and hydrophobic encapsulation layer is indispensable for stable and high-performance top-gated MoS2 transistors with mica gate dielectric. [ABSTRACT FROM AUTHOR]

In this work, we investigate the effects on the electrical properties of few-layered MoS2 field-effect transistors (FETs) following Al incorporation into ZrO2 as the gate dielectrics of the devices. A large improvement in device performance is achieved with the Al-doped ZrO2 gate dielectric when Zr:Al = 1:1. The relevant MoS2 transistor exhibits the best electrical characteristics: high carrier mobility of 40.6 cm2 V−1 s−1 (41% higher than that of the control sample, and an intrinsic mobility of 68.0 cm2 V−1 s−1), a small subthreshold swing of 143 mV dec−1, high on/off current ratio of 6 × 106 and small threshold voltage of 0.71 V. These are attributed to the facts that (i) Al incorporation into ZrO2 can decrease its oxygen vacancies; densify the dielectric film; and smooth the gate dielectric surface, thus reducing the traps at/near the Zr0.5Al0.5Oy/MoS2 interface and the gate leakage current; (ii) adjusting the dielectric constant of the gate dielectric to an appropriate value, which achieves a reasonable trade-off between the gate screening effect on the Coulomb-impurity scattering and the surface optical phonon scattering. These results demonstrate that optimized Zr0.5Al0.5Oy is a potential gate dielectric material for MoS2 FET applications. [ABSTRACT FROM AUTHOR]

For top-gated MoS2 field-effect transistors, damaging the MoS2 surface to the MoS2 channel are inevitable due to chemical bonding and/or high-energy metal atoms during the vacuum deposition of gate dielectric, thus leading to degradations of field-effect mobility (μFE) and subthreshold swing (SS). A top-gated MoS2 transistor is fabricated by directly transferring a 9 nm mica flake (as gate dielectric) onto the MoS2 surface without any chemical bonding, and exhibits excellent electrical properties with an on–off ratio of ∼108, a low threshold voltage of ∼0.2 V, a record μFE of 134 cm2 V−1 s−1, a small SS of 72 mV dec−1 and a low interface-state density of 8.8 × 1011 cm−2 eV−1, without relying on electrode-contact engineered and/or phase-engineered MoS2. Although the equivalent oxide thickness of the mica dielectric is in the sub-5 nm regime, enhanced stability characterized by normalized threshold voltage shift (1.2 × 10−2 V MV−1 cm−1) has also been demonstrated for the transistor after a gate-bias stressing at 4.4 MV cm−1 for 103 s. All these improvements should be ascribed to a damage-free MoS2 channel achieved by a dry transfer of gate dielectric and a clean and smooth surface of the mica flake, which greatly decreases the charged-impurity and interface-roughness scatterings. The proposed transistor with low threshold voltage and high stability is highly desirable for low-power electronic applications. [ABSTRACT FROM AUTHOR]

The effects of incorporating Al into HfO2 as gate dielectric on the back-gated MoS2 transistor are investigated. Hf0.5Al0.5O as gate dielectric exhibits excellent electrical characteristics: on/off ratio of 1.8 × 107, carrier mobility of 49.3 cm2/(V · s), subthreshold swing of 118 mV dec−1, interface-state density of 2.3 × 1012 eV−1 cm−2, due to the Al incorporation into the HfO2 can passivate the defective states induced by oxygen vacancies and improve the dielectric densification and uniformity to obtain an excellent MoS2/Hf1-xAlxO interface. Besides, the intrinsic carrier mobility of 100 cm2 V−1 s−1 and contact resistance of 11.1 kΩ/μm indicates that the contact resistance is a main factor limiting the mobility. [ABSTRACT FROM AUTHOR]

GaAs MOS capacitors with ZrLaON as the high-k dielectric layer and LaON as the interfacial passivation layer (IPL) are fabricated and the effects of the La content in ZrLaON on the device performance are investigated. Experimental results show that ZrLaON with a moderate or high La content induces serious moisture absorption, thus deteriorating the interfacial and electrical properties of the device, even with the LaON IPL. By adjusting the La content to a suitable value, e.g. a La/(La + Zr) atomic ratio of 13%, good interfacial and electrical properties can be obtained because the passivating role of La on the defects in ZrON can over-compensate the performance degradation induced by the moisture absorption. With the LaON IPL, further improvements in interfacial and electrical properties can be achieved because the LaON IPL can effectively passivate the As-O, Ga-O and As-As bonds at/near the high-k/GaAs interface. [ABSTRACT FROM AUTHOR]

The carrier mobility of MoS2 transistors can be greatly improved by the screening role of high-k gate dielectric. In this work, atomic-layer deposited (ALD) HfO2 annealed in NH3 is used to replace SiO2 as the gate dielectric to fabricate back-gated few-layered MoS2 transistors, and good electrical properties are achieved with field-effect mobility (μ) of 19.1 cm2 V–1 s–1, subthreshold swing (SS) of 123.6 mV dec–1 and on/off ratio of 3.76 × 105. Furthermore, enhanced device performance is obtained when the surface of the MoS2 channel is coated by an ALD HfO2 layer with different thicknesses (10, 15 and 20 nm), where the transistor with a 15 nm HfO2 encapsulation layer exhibits the best overall electrical properties: μ = 42.1 cm2 V–1 s–1, SS = 87.9 mV dec–1 and on/off ratio of 2.72 × 106. These improvements should be associated with the enhanced screening effect on charged-impurity scattering and protection from absorption of environmental gas molecules by the high-k encapsulation. The capacitance equivalent thickness of the back-gate dielectric (HfO2) is only 6.58 nm, which is conducive to scaling of the MoS2 transistors. [ABSTRACT FROM AUTHOR]

An equivalent distributed capacitance model is established by considering only the gate oxide-trap capacitance to explain the frequency dispersion in the C–V curve of MOS capacitors measured for a frequency range from 1 kHz to 1 MHz. The proposed model is based on the Fermi–Dirac statistics and the charging/discharging effects of the oxide traps induced by a small ac signal. The validity of the proposed model is confirmed by the good agreement between the simulated results and experimental data. Simulations indicate that the capacitance dispersion of an MOS capacitor under accumulation and near flatband is mainly caused by traps adjacent to the oxide/semiconductor interface, with negligible effects from the traps far from the interface, and the relevant distance from the interface at which the traps can still contribute to the gate capacitance is also discussed. In addition, by excluding the negligible effect of oxide-trap conductance, the model avoids the use of imaginary numbers and complex calculations, and thus is simple and intuitive. [ABSTRACT FROM AUTHOR]

Atomic layer deposited HfO2 annealed in different ambients (N2, O2, and NH3) is used to replace SiO2 as a gate dielectric for fabricating back-gated multilayer MoS2 transistors. Excellent electrical properties such as a mobility of 15.1 cm2/(V·s), an on/off ratio exceeding 107, and a hysteresis of 0.133 V are achieved for samples annealed in NH3 at 400 °C for 10 min. This is caused by the NH3 annealing passivation effects that reduce defective states in the HfO2 dielectric and the interface. The capacitance equivalent thickness is only 7.85 nm, which is quite small for a back-gated MoS2 transistor and is conducive to the scaling down of the device. [ABSTRACT FROM AUTHOR]

GaAs metal–oxide–semiconductor (MOS) capacitors with HfTiON as a gate dielectric and Ga2O3(Gd2O3) (GGO) as an interlayer annealed in NH3 or N2 are fabricated, and their electrical properties are characterized. Experimental results show that the HfTiON/GGO/GaAs MOS device annealed in NH3 exhibits a low interface-state density (1.1 × 1012 cm−2 eV−1), a small gate leakage current (1.66 × 10−4 A cm−2 at Vg = Vfb + 1 V), a large equivalent dielectric constant (25.7), and a good capacitance–voltage behavior. All these should be attributed to the fact that the GGO interlayer and postdeposition annealing in NH3 can effectively suppress the formation of interfacial Ga/As oxides and remove the excess As atoms at the GaAs surface, thus reducing the relevant defects at/near the GGO/GaAs interface. [ABSTRACT FROM AUTHOR]