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We present results on low-pressure chemical vapor deposition (LPCVD) of β-Ga2O3 on a c-sapphire substrate with independent control of Ga precursor (T P) and substrate (T SUB) temperatures, allowing independent tuning of the Ga flux and thermal energy of the adatoms on the substrate surface. Experiments with constant T P = 900 °C with varying T SUB (600 °C–1050 °C) and varying T P (800 °C–1000 °C) with constant T SUB = 900 °C are reported. Island/nanorod formation on top of β-Ga2O3 thin film was observed at T SUB = 600–750 °C, suggesting the Stranski–Krastanov mode of growth, while thin film growth was observed for T SUB = 825–1050 °C. The growth rate decreased at higher T SUB, whereas it increased sharply for T P = 800–850 °C followed by a quasi-saturation for T P = 800–1000 °C. The growth rate evolution in both experiments reveals the significant role of gallium suboxide formation and desorption at the precursor/film during β-Ga2O3 LPCVD. This study provides useful insights into the growth dynamics involved in LPCVD of β-Ga2O3.

In this paper, we present the modeling of zero-threshold voltage (V TH) bulk MOSFET, also called native devices, using enhanced BSIM6 model. Devices under study show abnormally high leakage current in weak inversion, leading to degraded subthreshold slope. The reasons for such abnormal behavior are identified using technology computer-aided design (TCAD) simulations. Since the zero-V TH transistors have quite low doping, the depletion layer from drain may extend upto the source (at some non-zero value of V DS) which leads to punch-through phenomenon. This source–drain leakage current adds with the main channel current, causing the unexpected current characteristics in these devices. TCAD simulations show that, as we increase the channel length (L eff) and channel doping (N SUB), the source–drain leakage due to punch-through decreases. We propose a model to capture the source–drain leakage in these devices. The model incorporates gate, drain, body biases and channel length as well as channel doping dependency too. The proposed model is validated with the measured data of production level device over various conditions of biases and channel lengths.

In this paper, self-consistent three-dimensional (3D) device simulations for exact analysis of thermal transport in FinFETs are performed. We analyze the temperature rise in FinFET devices with the variation in the number of fins (N fin), shape of fins and fin pitch (F pitch). We investigate that the thermal resistance R th has nonlinear dependency on N fin and F pitch. We formulate a model for thermal resistance behavior correctly with N fin and F pitch variation. The proposed formulation is implemented in industry standard Berkeley short-channel independent gate FET model for common multi-gate transistors (BSIM-CMG) and validated with both experimental data and TCAD simulations.