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To achieve stable operations of high-Tc superconducting (HTS) single-flux-quantum circuits, we have studied the reproducibility and uniformity of inductances for HTS striplines. Optimizing a fabrication process of the striplines, the sheet inductances of the striplines for four samples were ranged from 0.77 to 0.93 pH per square at 4.2 K. The differences between these values and a designed value (Ld) of the sheet inductance were less than 10% of Ld. A 4 h oxygen annealing at 450 °C in 1 atm oxygen decreased the 1σ-spread of the stripline inductances from 12 to 4.9% at 4.2 K. It was found that taking into account the reproducibility and spread of inductances, the designed value of the sheet inductance should be less than 0.8 pH/ in order to obtain low inductance (less than 1 pH/) in a circuit area.

We fabricated and tested a high-temperature superconducting (HTS) sigma–delta modulator using interface-engineered Josephson junctions. Proper dc-characteristics were obtained with a sampling frequency of 100 GHz at 20 K. To achieve high-speed sampling, Josephson junctions with a higher critical-current normal-resistance product were used. Circuit simulations with thermal noise were performed for the analysis of switching characteristics and SFQ dynamics.

We have developed a multilayer process for fabricating crossover and via structures. A crossover structure with Tc>85 K was fabricated by using an SrTiO3 buffer layer to repair the SrTiO3 surface damaged during etching. The interlayer resistance of a 10 µm × 50 µm crossover area was 150 k. Via contacts fabricated under various process conditions all showed residual resistance with reduced Tc, indicating the formation of damaged layers at the contact interfaces. However, the Ic measured through the via contacts fabricated under the optimal conditions exceeded 3 mA at 77 K which was high enough for most superconducting device applications.

We have developed and tested a new circuit simulation procedure for superconducting integrated circuits which can be used to optimize circuit parameters. This method reveals a stable operation region in the circuit parameter space in connection with the global bias margin by means of a contour plot of the global bias margin versus the circuit parameters. An optimal set of parameters with margins larger than these of the initial values has been found in the stable region.