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An n-channel 4H-SiC insulated-gate bipolar transistor (IGBT) with an extremely low switching loss was demonstrated by making 70 μm thin drift layers designed for 6.5 kV blocking voltage, without substrates. A conductivity-modulated bipolar operation was successfully performed as a on-voltage of 4.96 V at a 100 A cm−2 collector current. The turn-off losses under 3.6 kV/32 A operation were 8.8 (at room temperature) and 22.7 mJ (at 150 °C), which were much lower than the estimated losses of SiC IGBTs with thick drift layers. A detailed investigation on turn-off transition of SiC IGBTs specifically focused on a voltage-slope increase was also conducted. This phenomenon can cause ringing in switching characteristics. A device structure has been proposed to eliminate it by controlling the expansion of a depletion layer. Voltage-slope control and ringing reduction without noticeable degradation in static characteristics and switching loss were demonstrated with the SiC IGBT with the proposed device structure.

High-temperature reverse bias (HTRB) and high-humidity HTRB (H3TRB) tests were carried out on 4H-SiC diodes to investigate the mechanism of charge accumulation at the SiO2/SiC interface in the edge termination area, which causes breakdown voltage. To analyze the distribution of charge density during these tests, a differentiated capacitance-reverse-voltage method was used. From comparing the results of the HTRB and H3TRB tests, it was clarified that the H3TRB test induces negative charge at the SiO2/SiC interface but induces positive charge at the polyimide/SiC interface. We concluded that the origin of the increase in charge density induced by high-humidity stress is the corrosion of the anode metal, which depends on the surface film of the SiC in the termination area, namely, the SiO2/SiC or polyimide/SiC interface. The induced charge mechanism can become a guideline for designing highly reliable SiC power devices against humidity stress.

Process-induced basal plane dislocations (BPDs) formed by annealing after aluminum ion implantation were investigated, and their effect on the bipolar degradation of body diodes in 3.3 kV SiC MOSFETs was evaluated. Contact resistance in the p+ region decreases with ion dose but increases with implantation temperature due to the formation of the recrystallized layer at SiC surface and difference of acceptor activation rates in high and low temperature implantation. In the case of high ion dose implantation at room temperature, contact resistance was of 1.3 × 10−3 Ωcm2. However, process-induced BPDs formed with high ion dose implantation at room temperature, and could be suppressed with low ion dose or high implantation temperature. They were formed after activation annealing, and expanded to form stacking faults (SFs) under both continuous irradiation from a Hg lamp and current stress. Bipolar degradation occurred in the case of MOSFETs fabricated using high ion dose implantation at room temperature, but was not observed in the case of either low ion dose or high implantation temperature. The activation energy for SF expansion velocity in the 〈1–100〉 direction was estimated to be 0.20 eV at a forward current density of 125 A cm−2. Moreover, the results of a long duration current stress test with high current density and high junction temperature indicate that low ion dose or high implantation temperature can suppress the formation of process-induced BPDs. MOSFETs fabricated using optimized ion implantation conditions show high reliability under bipolar operation.

Top-gated devices made from an epitaxial graphene film on a 4H-SiC substrate were fabricated. Atomic force microscopy and Raman spectroscopy results showed that a large-scale highly uniform monolayer graphene film was synthesized on the SiC substrate. A SiN x passivation film was deposited on a SiC graphene device as a top gate insulator by catalytic chemical-vapor deposition (Cat-CVD) below 65 °C. After the top gate electrode was formed on the SiN x film, no leakage current flowed between the gate and source electrodes. The transport characteristics showed clear ambipolar characteristics from 8 to 280 K, and the temperature dependences of the conductance and field-effect mobility of the devices implied that monolayer graphene devices can be successfully fabricated. Moreover, the position of the charge neutrality point after SiN x deposition was around 0 V, indicating p-doping characteristics. These results indicate that SiN x films synthesized by Cat-CVD can be used as gate insulators and that the carrier type may be controlled by adjusting the deposition conditions.

The negative bias temperature instability in SiC MOSFETs was investigated. Considering the time, temperature, and bias dependences of the threshold-voltage (Vth) shift, we propose a two-component model for long-term prediction. On the basis of fitting results, we discuss the origins of these components. The first component, which dominates short-term instability, was found to show reverse temperature and weak bias dependences. Such trends are consistent with the carrier exchange of pre-existing slow oxide traps, which are O vacancies. After subtracting the first component, the second component was found to show power-law time dependence, similar to that observed in Si devices. The forward temperature and strong bias dependences of the second component indicate the activation of additional traps. The activation energy of 0.1 eV is consistent with that of a Si device using nitrided gate oxide. Therefore, the origin of the long-term Vth shift of SiC-MOSFETs was suggested to be a nitrogen-related site. Control of the amount of nitrogen is expected to be important for the long-term threshold stability of SiC-MOSFETs.

Dynamic fluctuation in stress-induced leakage current, called V-SILC, which is one of the causes of erratic bits in flash memory, was investigated. This investigation showed that V-SILC is attributed to random telegraph noise, which is associated with a state transition of a single defect. To analyze the mechanism of the state transition, dependences of state-transition probabilities on gate current and temperature were investigated. These dependences indicate that the state transitions are caused by current injection, and the mechanism of the state transition causing V-SILC is a defect-structure transition caused by charge collision.

Dynamic fluctuation in stress-induced leakage current – called “variable stress-induced leakage current” – in a gate oxide of a metal–oxide–semiconductor structure was investigated. Variable stress-induced leakage current is attributed to random telegraph noise, which is associated with the state-transition of a single defect. To analyze the mechanism of the state-transition, dependence of state-transition probabilities on gate current and on temperature were investigated. These dependences indicate that the state-transition mechanism is a defect-structure transition by charge collision.

It was experimentally found that an interface state causes variable junction leakage (VJL), namely, random telegraph noise in a reverse-biased junction leakage current which is one result of off-state drain leakage in metal–oxide–semiconductor field-effect transistors (MOSFETs). We prepared deep-submicron-scale MOSFETs of which the defect densities of the Si/SiO2 interface were controlled by the annealing conditions. It was confirmed that the occurrence rate of VJL changes with the density of interface states. Furthermore, it was shown that the mechanism of VJL is similar to that of random telegraph noise (RTN) in drive current.

Fluctuations in not only the number but also the individual electronic properties of interface traps in small-gate-area metal–oxide–semiconductor field-effect transistors (MOSFETs) containing just a few interface traps have been directly observed. This observation is based on an understanding of a newly observed phenomenon in the charge pumping characteristics, i.e., on-time (or off-time)-dependent charge pumping characteristics. It is shown that the fluctuation in the number of interface traps contained in an individual MOSFET is fairly large, and that there are various interface traps with individual carrier capture rates. These fluctuations may have an impact on the variation in threshold voltage of future digital metal–insulator–semiconductor devices.