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2D materials offer a pathway for further scaling of CMOS technology. However, for this to become a reality, both n-MOS and p-MOS should be realized, ideally with the same (standard) material. In the specific case of MoS2 field effect transistors (FETs), ambipolar transport is seldom reported, primarily due to the phenomenon of Fermi level pinning (FLP). In this study we identify the possible sources of FLP in MoS2 FETs and resolve them individually. A novel contact transfer technique is used to transfer contacts on top of MoS2 flake devices that results in a significant increase in the hole branch of the transfer characteristics as compared to conventionally fabricated contacts. We hypothesize that the pinning not only comes from the contact-MoS2 interface, but also from the MoS2-substrate interface. We confirm this by shifting to an hBN substrate which leads to a 10 fold increase in the hole current compared to the SiO2 substrate. Furthermore, we analyse MoS2 FETs of different channel thickness on three different substrates, SiO2, hBN and Al2O3, by correlating the p-branch ION/IOFF to the position of oxide defect band in these substrates. FLP from the oxide is reduced in the case of Al2O3 which enables us to observe ambipolar transport in a bilayer MoS2 FET. These results highlight that MoS2 is indeed an ambipolar material, and the absence of ambipolar transport in MoS2 FETs is strongly correlated to its dielectric environment and processing conditions. [ABSTRACT FROM AUTHOR]

Carbon nanotubes (CNTs) are considered a promising material for interconnects for future generation microchips. The integration of vertical CNT in a processing environment is evaluated in this work. Extrapolated performances of CNT-based interconnects are compared with existing technologies at different hierarchy levels including the limitations of present deposition methods for copper and tungsten. For practical implementation, CNT bundles were selectively grown into contact holes using physical vapor deposited and electrochemical deposited cobalt or nickel catalysts. A polishing step was used to control the CNT length after embedding the CNT into an oxide matrix. A CNT metal decoration method based on electrodeposition is presented, which can be used to assess the yield of electrically conductive CNT as well as to form top contacts for electrical characterization. Finally, the importance of having suitable and robust Structures for evaluating the integration process is highlighted after the electrical characterization of CNT in a nanoprober station. [ABSTRACT FROM AUTHOR]

Electrodeposition is an excellent method for a site-selective and direct fabrication of catalyst nanoparticles for subsequent carbon nanotube (CNT) growth. Nickel nanoparticles with densities as high as 1011 cm-2 and diameters down to 15 ± 4 nm are deposited on blanket and pattemed TiN wafers. Ni nanoparticles are selectively placed at the bottom of submicrometer vias by through-mask electrodeposition. The spherical nanoparticles all produce aligned multiwalled CNTs. The CNT diameter is directly determined by the diameter of the as-deposited nanoparticles, which is tailored by the electrodeposition conditions. Such control of CNT size, density, and location represents an important step toward the implementation of CNTs in device fabrication. [ABSTRACT FROM AUTHOR]

The downscaling of highk/metal gate transistor devices requires thinfilm deposition processes that deliver not only an outstand ing highk oxide quality, but also a strict interfacial oxide thickness control in the subI nm thickness range. To study the impact of atomic layer deposition (ALD) process conditions and chemistry on the HfO2 quality and interfacial oxide thickness, we have used tetrakis[ethylmethylamino]hafnium (TEMAH) as a metal precursor and H2O and O3 as oxidants. The deposition temperature ranged from 285 up to 365°C, where TEMAH decomposition plays a role in the growth mechanism. Physical characterization and Pt dot capacitor devices have been used to study the impact of the oxidant and process conditions on the equivalent oxide thickness and gate leakage current of 24 nm thin HfO2 films. By combining Xray reflectometry and ellipsometry, we evaluated the Si/highk interfacial oxide layer thickness. Timeofflight secondaryion mass spectroscopy was used to determine the C impurity levels. Both the interfacial oxide layer thickness and the C impurity level in the Si/SiO2/HfO2 stacks are strongly dependent on the oxidant. The temperature dependence of the C impurity level is opposite for O3 and H2O. Furthermore, SiO2 regrowth was found for the O3 process. [ABSTRACT FROM AUTHOR]

The role of moisture (H[sub2]O) in atomic-layer-deposited (ALD) HfO[sub2∙] and HfSiO[sub2∙] dielectrics on equivalent oxide thickness (EOT) scaling is investigated in gate-first devices with physical-vapor-deposited TaN gates. By reducing the amount of H[sub2]O present in the gate stack, the EOT increase during high-temperature (1030°C) spike annealing is reduced from 0.5 to0.25 nm. This was achieved by a premetallization degas at 350-550°C for 3 mm. The origin of this improvement lies in the elimination of H[sub2]O-related reoxidation of the interfacial SiO[sub2]. By means of temperature-programmed desorption measurements, it is found that the majority of the H[sub2]O is desorbed between 200 and 600°C with activation energies between ∼0.3 and -0.5 eV. Furthermore, the H[sub2]O concentration is dependent on the Hf concentration and nitridation. Non-nitrided HfSiO[sub2∙] with [Hf] = 40% adsorbs twice as much H[sub2]O as HfO[sub2∙]. Correspondingly, a significantly larger FOT increase is observed for HfSiO[sub2∙] with [Hf] 40% as compared to HfO[sub2∙]. In HfSiON, the desorbed H[sub2]O concentration is independent of [Hf]. Finally, a strong metal dependency on the EOT regrowth is observed. With ALD TiN, the EOT increase after thermal treatment is found to be independent of the degas condition at ∼0.2 nm. [ABSTRACT FROM AUTHOR]

In this work, we studied molybdenum (Mo) and its conductive oxides (MoOx) for p-type metal gate application. Three compositions of MoOx have been investigated. The resistivity of Mo/MoOx was found to significantly increase with the oxygen incorporation. A clear phase separation of all MoOx compositions was observed after high-temperature thermal treatment. The incorporation of oxygen was found to be effective to increase the work function (WF) of Mo. However, after full device integration, a significant WF decrease of MoOx was observed, which may be induced during the high-temperature junction activation process. This high-temperature process also led to a significant interfacial silicon oxide layer growth for MoOx gated stacks. The equivalent oxide thickness dependent flatband voltage roll-off behavior and gate leakage will also be discussed. [ABSTRACT FROM AUTHOR]