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An embedded 3D graphics rendering engine (E3GRE) is implemented as a part of a mobile PDA-chip. 6 Mb embedded DRAM (eDRAM) macros attached to 8-pixel-parallel rendering logic are logically localized with 3.2 GByte/s runtime reconfigurable bus, by which the area is reduced by 25%. Polygon-dependent access to eDRAM macros with line-block mapping reduces the power consumption by 70% with the read-modify-write data transaction. E3GRE with 2.22 M polygons/s drawing speed was fabricated using 0.18 /spl mu/m CMOS embedded memory logic technology. Its area and power consumption are 24 mm/sup 2/ and 120 mW, respectively.

A 16.3 mW low power motion compensation (MC) block IP with 1.25 Mbit embedded DRAM macro is implemented using 0.18 /spl mu/m EML technology for portable video applications. For low power consumption, its frequency is lowered to 20 MHz by utilizing parallelism in datapath. Embedded DRAM frame buffer eliminates external data I/O. In addition, distributed nine-tiled mapping (DNTM) with partial activation scheme reduces power for accessing the frame buffer up to 31% compared to conventional 1-bank tiled mapping. Adaptive fetch control (AFC) in data buffer reduces power up to 29% by eliminating unnecessary switching in datapath.