1. Effects of power-supply parasitic components on substrate noise generation in large-scale digital circuits
- Author
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Takafumi Ohmoto, Y. Hlurasaka, Takashi Morie, Atsushi Iwata, and Makoto Nagata
- Subjects
Digital electronics ,Engineering ,Substrate coupling ,business.industry ,Electrical engineering ,Mixed-signal integrated circuit ,Hardware_PERFORMANCEANDRELIABILITY ,Noise (electronics) ,Integrated injection logic ,CMOS ,Hardware_INTEGRATEDCIRCUITS ,Electronic engineering ,Flicker noise ,Parasitic extraction ,business ,Hardware_LOGICDESIGN - Abstract
Activity controllable noise source and arrayed substrate voltage detectors use a 0.25-/spl mu/m, 2.5-V CMOS technology and enable substrate noise measurements with controlled logic density/activity distributions. These circuits are used for exploring effects of power-supply parasitic components on substrate noise generation in practical large-scale CMOS digital circuits. Spatially distributed parasitic impedances on power-supply and return wirings cause the noise generation locally, and moreover, screen the effect of noise attenuation by parasitic capacitances of logic elements working as charge reservoirs.
- Published
- 2002
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