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Vacuum and hermetic packaging is a critical requirement for optimal performance of many micro-electro-mechanical systems (MEMS), vacuum electronics, and quantum devices. However, existing packaging solutions are either elaborate to implement or rely on bulky caps and footprint-consuming seals. Here, we address this problem by demonstrating a wafer-level vacuum packaging method featuring transfer bonding of 25-μm-thin silicon (Si) caps that are transferred from a 100-mm-diameter silicon-on-insulator (SOI) wafer to a cavity wafer to seal the cavities by gold-aluminum (Au-Al) thermo-compression bonding at a low temperature of 250 °C. The resulting wafer-scale sealing yields after wafer dicing are 98% and 100% with sealing rings as narrow as 6 and 9 μm, respectively. Despite the small sealing footprint, the Si caps with 9-μm-wide sealing rings demonstrate a high mean shear strength of 127 MPa. The vacuum levels in the getter-free sealed cavities are measured by residual gas analysis to be as low as 1.3 mbar, based on which a leak rate smaller than 2.8x10-14 mbarL/s is derived. We also show that the thickness of the Si caps can be reduced to 6 μm by post-transfer etching while still maintaining excellent hermeticity. The demonstrated ultra-thin packages can potentially be placed in between the solder bumps in flip-chip interfaces, thereby avoiding the need of through-cap-vias in conventional MEMS packages., QC 20190619

The energy consumption of field-programmable gate arrays (FPGA) is dominated by leakage currents and dynamic energy associated with programmable interconnect. An FPGA built entirely from nanoelectromechanical (NEM) relays can effectively eliminate leakage energy losses, reduce the interconnect dynamic energy, operate at temperatures >225 °C and tolerate radiation doses in excess of 100 Mrad, while hybrid FPGAs comprising both complementary metal-oxide-semiconductor (CMOS) transistors and NEM relays (NEM-CMOS) have the potential to realize improvements in performance and energy efficiency. Large-scale integration of NEM relays, however, poses a significant engineering challenge due to the presence of moving parts. We discuss the design of FPGAs utilizing NEM relays based on a heterogeneous 3-D integration scheme, and carry out a scaling study to quantify key metrics related to performance and energy efficiency in both NEM-only and NEM-CMOS FPGAs. We show how the integration scheme has a profound effect on these metrics by changing the length of global wires. The scaling regime beyond which net performance and energy benefits is seen in NEM-CMOS over a baseline 90 nm CMOS technology is defined by an effective relay beam length of 0.5 μm , on-resistance of 200 kΩ , and a via pitch of 0.4 μm , all achievable with existing process technology. For ultra-low energy applications that are not performance critical, NEM-only FPGAs can provide close to 15× improvement in energy efficiency., QC 20180412

Wafer-level vacuum packaging is vital in the fabrication of many microelectromechanical systems (MEMS) devices and enables significant cost reduction in high-volume MEMS production. In this paper, we propose a low-temperature wafer-level vacuum packaging method based on plastic deformation and low-temperature welding of copper sealing rings with a small footprint. A device wafer with copper ring structures and a cap wafer with corresponding metalized grooves are placed inside a vacuum chamber and pressed together at a temperature of 250 ̊C, resulting in low-temperature welding of the copper, and thus, hermetic sealing of the cavities enclosed by the sealing rings. The vacuum pressure inside the fabricated cavities 146 days after bonding was measured using residual gas analysis to be as low as 2.6×10-2 mbar. Based on this value, the leak rate is calculated to be smaller than 3.6×10-16 mbarL/s using the most conservative assumptions, demonstrating the excellent hermeticity of the seals. Shear testing was used to demonstrate that the seals are mechanically stable with over 90 MPa in shear strength for 5.2 μm-high Cu sealing rings with widths down to 8 μm. The reported method is potentially compatible with complementary metaloxide-semiconductor (CMOS) substrates and may be applied to vacuum packaging of 3-D heterogeneously integrated MEMS on state-of-the-art CMOS substrates., QC 20170516When citing this work, please cite the original published paper.