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This special section is composed of substantially extended handpicked papers from the IEEE Nordic Circuits and Systems Conference (NorCAS) 2022 that took place in October 2022 in Oslo, Norway.

Pushing CMOS technology to the nanometer range is detrimental to analog circuits’ performance due to the reduction of gain and slew rate of amplifiers, so the classical approaches need to be revisited for adjustment in advanced nodes. This paper presents a parallel-path amplifier used as a switched-capacitor (SC) amplifier. The proposed amplifier includes a high bandwidth and slewing path parallel to a high gain path. The high bandwidth and slewing path, named the feedforward path, provides high charging/discharging currents to decrease the slewing time of the amplification phase, significantly (60%). In parallel, the high gain path provides sufficient open-loop DC gain for final settling (59 dB). The feedforward path is enabled/disabled by control signals provided through a hysteresis detector and by considering the status of the feedback voltage. The proposed amplifier is designed and fabricated in 65nm CMOS technology as a multiplying digital-to-analog converter (MDAC) in a pipeline ADC. The chip is under fabrication, and this paper covers post-layout performance of the proposed amplifier. The results reveal that enabling the feedforward path guarantees the amplifier to have a constant error (\lt2 mV) for an extensive range of input voltages (300 mV Vin 900 mV) compared to its standalone high gain path. At the same time, the static current of the feedforward path is minimal (\lt 100 µ A), and it can drive large load capacitors. © 2023 IEEE., Funding: Excellence Center at Linkoping-Lund in Information Technology (ELLIIT)

Extending the wireless power transfer range in miniaturized remotely powered micro-devices is a big challenge due to the very small effective area and low gain of the mm-sized antenna utilized in the micro-devices, which limits the harvested RF energy. This paper presents a method for increasing the separation distance between an external energy source antenna as a transmitter (TX) and micro device antenna as a receiver (RX) beyond 10 cm by utilizing various TX antennas, including a conventional loop antenna, multiple patch antennas, and a rectangular cavity antenna, and a 2-turn double-sided square loop RX antenna, sized 1.2mm x 1.2mm on FR4 substrate, which can be mounted on top of a CMOS SoC. The performance of the wireless power transfer system is evaluated and compared in different scenarios. At the 434 MHz ISM band, the results indicate that the highest peak power transfer efficiency of -20 dB and the highest harvested DC voltage of 4 V through an 8-stage Dickson RF-DC converter are obtained inside the rectangular hollow cavity sized 49.6cm x 49.6cm x 30.4cm, as TX, with an input TX power of 20 dBm. Furthermore, the multiple patch antennas have a power transfer efficiency of -39 dB and a harvested DC voltage of 2.5 V at a distance of 10 cm with an input TX power of 37 dBm. The specific absorption rate of both cases stays below the limits established by IEEE., Funding Agencies|Swedish Foundation for Strategic Research (SSF) [RMX18-0066]

This paper involves the design and integration of an ultra-low power consumption Amplitude Shift Keying (ASK) demodulator and a digital Manchester decoder for biomedical applications. The ASK demodulator is based on a common source (CS) self-biased envelope detector (ED) with a double feedback loop, succeeded by a static comparator featuring constant transistor bias with a native transistor. While the digital Manchester decoder performs clock and data recovery. The practical implementation of the work is validated through simulations, executed on a standard 65 nm CMOS technology with a 50 Kbps data rate and a carrier frequency of 570 MHz. The average current drawn from a 2.5 V power supply is less than 800 nA while the circuit operates under RF variations and modulation indices ranging from 13.5% to 100%., Funding Agencies|Swedish Foundation for Strategic Research (SSF) [RMX18-0066]

This paper proposes an all-pass filter-based true time delay (TTD) element covering a 3-5-GHz ultra-wideband (UWB) frequency. The proposed TTD element designed in a standard 0.18-mu m CMOS technology achieves a tunable delay range of 385-540 ps with 6-ps delay steps and maximum 11% absolute delay error over a 3-5-GHz frequency band. It exhibits an average 3.6-4.6-dB noise figure (NF) within the whole bandwidth. A four-channel beamforming receiver realized by the proposed TTD element is designed and examined in this paper, as well. With the maximum delay of 540 ps and 6-ps average delay resolution, a maximum steering angle of +/- 45 degrees with 5 degrees (18 steps) steering resolution is demonstrated for the beamforming receiver with 2-cm antenna spacing.