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Internet of Things (IoT) enabled devices have become more and more pervasive in our everyday lives. Examples include wearables transmitting and processing personal data and smart labels interacting with customers. Due to the sensitive data involved, these devices need to be protected against attackers. In this context, hardware-based security primitives such as Physical Unclonable Functions (PUFs) provide a powerful solution to secure interconnected devices. The main benefit of PUFs, in combination with traditional cryptographic methods, is that security keys are derived from the random intrinsic variations of the underlying core circuit. In this work, we present a holistic analog-based PUF evaluation platform, enabling direct access to a scalable design that can be customized to fit the application requirements in terms of the number of required keys and bit width. The proposed platform covers the full software and hardware implementations and allows for tracing the PUF response generation from the digital level back to the internal analog voltages that are directly involved in the response generation procedure. Our analysis is based on 30 fabricated PUF cores that we evaluated in terms of PUF security metrics and bit errors for various temperatures and biases. With an average reliability of 99.20% and a uniqueness of 48.84%, the proposed system shows values close to ideal. [ABSTRACT FROM AUTHOR]

Low power, low cost inductively powered passive biotelemetry system involving fully customized RFID/NFC interface base SoC has gained popularity in the last decades. However, most of the SoCs developed are application specific and lacks either on-chip computational or sensor readout capability. In this paper, we present design details of a programmable passive SoC in compliance with ISO 15693/NFC5 standard for biomedical applications. The integrated system consists of a 32-bit microcontroller, a sensor readout circuit, a 12-bit SAR type ADC, 16 kB RAM, 16 kB ROM and other digital peripherals. The design is implemented in a 0.18 µm CMOS technology and used a die area of 1.52 mm x 3.24 mm. The simulated maximum power consumption of the analog block is 592 µW. The number of external components required by the SoC is limited to an external memory device, sensors, antenna and some passive components. The external memory device contains the application specific firmware. Based on the application, the firmware can be modified accordingly. The SoC design is suitable for medical implants to measure physiological parameters like temperature, pressure or ECG. As an application example, the authors have proposed a bioimplant to measure arterial blood pressure for patients suffering from Peripheral Artery Disease (PAD). [ABSTRACT FROM AUTHOR]

Battery-less passive sensor tags based on RFID or NFC technology have achieved much popularity in recent times. Passive tags are widely used for various applications like inventory control or in biotelemetry. In this paper, we present a new RFID/NFC frontend IC (integrated circuit) for 13.56 MHz passive tag applications. The design of the frontend IC is compatible with the standard ISO 15693/NFC 5. The paper discusses the analog design part in details with a brief overview of the digital interface and some of the critical measured parameters. A novel approach is adopted for the demodulator design, to demodulate the 10% ASK (amplitude shift keying) signal. The demodulator circuit consists of a comparator designed with a preset offset voltage. The comparator circuit design is discussed in detail. The power consumption of the bandgap reference circuit is used as the load for the envelope detection of the ASK modulated signal. The sub-threshold operation and low-supply-voltage are used extensively in the analog design—to keep the power consumption low. The IC was fabricated using 0.18 μ m CMOS technology in a die area of 1.5 mm × 1.5 mm and an effective area of 0.7 m m 2 . The minimum supply voltage desired is 1.2 V, for which the total power consumption is 107 μ W. The analog part of the design consumes only 36 μ W, which is low in comparison to other contemporary passive tags ICs. Eventually, a passive tag is developed using the frontend IC, a microcontroller, a temperature and a pressure sensor. A smart NFC device is used to readout the sensor data from the tag employing an Android-based application software. The measurement results demonstrate the full passive operational capability. The IC is suitable for low-power and low-cost industrial or biomedical battery-less sensor applications. A figure-of-merit (FOM) is proposed in this paper which is taken as a reference for comparison with other related state-of-the-art researches. [ABSTRACT FROM AUTHOR]

Printed electronic devices have demonstrated their applicability in complex electronic circuits. There is recent progress in the realization of neuromorphic computing systems (NCSs) to implement basic synaptic functions using solution-processed materials. However, a fully printed neuron is yet to be realised. We demonstrate a fully printed artificial neuromorphic circuit on flexible polyimide (PI) substrate. Characteristic features of individual components of the printed system were guided by the software training of the NCS. The printing process employs graphene ink for passive structures and In2O3 as active material to print a two-input artificial neuron on PI. To ensure a small area footprint, the thickness of graphene film is tuned to target a resistance and to obtain conductors or resistors. The sheet resistance of the graphene film annealed at 300 °C can be adjusted between 200 Ω and 500 kΩ depending on the number of printed layers. The fully printed devices withstand a minimum of 2% tensile strain for at least 200 cycles of applied stress without any crack formation. The area usage of the printed two-input neuron is 16.25 mm2, with a power consumption of 37.7 mW, a propagation delay of 1 s, and a voltage supply of 2 V, which renders the device a promising candidate for future applications in smart wearable sensors.

Printing technology and mounting technology enable the novel field of hybrid printed electronics. To establish a hybrid printed system, one challenge is that the applied mounting process meets the requirements of functional inks and substrates. One of the most common requirements is low process temperature. Many functional inks and substrates cannot withstand the high temperatures required by traditional mounting processes. In this work, a standardized interconnection and an automated bump-less flip-chip mounting process using a room temperature curing conductive adhesive are realised. With the proposed process, the conductive adhesive selected for the standardized interconnection can be dispensed uniformly, despite its increase of viscosity already during pot time. Electrical and mechanical performance of the interconnection are characterized by four terminal resistance measurement and shear test. The herein proposed automated process allows for fabrication of hybrid printed devices in larger batch sizes than manual assembly processes used beforehand and thus, more comprehensive evaluation of device parameters. This is successfully demonstrated in a first application, a novel hybrid printed security device. The room temperature mounting process eliminates any potentially damaging thermal influence on the performance of the printed circuits that might result from other assembly techniques like soldering.