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Moreover, the memristor-based third-order circuit with two energy storage elements, a capacitor and an inductor, can produce complex chaotic oscillation, forming the simplest chaotic circuit. The memristor is considered to be a promising candidate for next-generation computing systems due to its nonvolatility, high density, low power, nanoscale geometry, nonlinearity, binary/multiple memory capacity, and negative differential resistance. Finally, the circuit simulation results verify the effectiveness of theoretical analyses and mathematical simulation and further illustrate the feasibility of the two-neuron-based memristive Hopfield neural network hardware. [Extracted from the article]

The rapid development of smart factories, combined with the increasing complexity of production equipment, has resulted in a large number of multivariate time series that can be recorded using sensors during the manufacturing process. The anomalous patterns of industrial production may be hidden by these time series. Previous LSTM-based and machine-learning-based approaches have made fruitful progress in anomaly detection. However, these multivariate time series anomaly detection algorithms do not take into account the correlation and time dependence between the sequences. In this study, we proposed a new algorithm framework, namely, graph attention network and temporal convolutional network for multivariate time series anomaly detection (GTAD), to address this problem. Specifically, we first utilized temporal convolutional networks, including causal convolution and dilated convolution, to capture temporal dependencies, and then used graph neural networks to obtain correlations between sensors. Finally, we conducted sufficient experiments on three public benchmark datasets, and the results showed that the proposed method outperformed the baseline method, achieving detection results with F1 scores higher than 95% on all datasets. [ABSTRACT FROM AUTHOR]

As the acquisition, transmission, storage and conversion of images become more efficient, image data are increasing explosively. At the same time, the limitations of conventional computational processing systems based on the Von Neumann architecture continue to emerge, and thus, improving the efficiency of image processing has become a key issue that has bothered scholars working on images for a long time. Memristors with non-volatile, synapse-like, as well as integrated storage-and-computation properties can be used to build intelligent processing systems that are closer to the structure and function of biological brains. They are also of great significance when constructing new intelligent image processing systems with non-Von Neumann architecture and for achieving the integrated storage and computation of image data. Based on this, this paper analyses the mathematical models of memristors and discusses their applications in conventional image processing based on memristive systems as well as image processing based on memristive neural networks, to investigate the potential of memristive systems in image processing. In addition, recent advances and implications of memristive system-based image processing are presented comprehensively, and its development opportunities and challenges in different major areas are explored as well. By establishing a complete spectrum of image processing technologies based on memristive systems, this review attempts to provide a reference for future studies in the field, and it is hoped that scholars can promote its development through interdisciplinary academic exchanges and cooperation. [ABSTRACT FROM AUTHOR]

In this paper, a fractional-order memristive model with infinite coexisting attractors is investigated. The numerical solution of the system is derived based on the Adomian decomposition method (ADM), and its dynamic behaviors are analyzed by means of phase diagrams, bifurcation diagrams, Lyapunov exponent spectrum (LEs), dynamic map based on SE complexity and maximum Lyapunov exponent (MLE). Simulation results show that it has rich dynamic characteristics, including asymmetric coexisting attractors with different structures and offset boosting. Finally, the digital signal processor (DSP) implementation verifies the correctness of the solution algorithm and the physical feasibility of the system. [ABSTRACT FROM AUTHOR]

In this work, three different RRAM compact models implemented in Verilog-A are analyzed and evaluated in order to reproduce the multilevel approach based on the switching capability of experimental devices. These models are integrated in 1T-1R cells to control their analog behavior by means of the compliance current imposed by the NMOS select transistor. Four different resistance levels are simulated and assessed with experimental verification to account for their multilevel capability. Further, an Artificial Neural Network study is carried out to evaluate in a real scenario the viability of the multilevel approach under study. [ABSTRACT FROM AUTHOR]

In the application of a long series battery group, an inter-pack imbalance is inevitable. No intra-pack cell equalizer can prevent pack-level over-discharge. A bimodal, multichannel battery pack equalizer based on a quasi-resonant, two-transistor forward converter is proposed to solve this problem and achieve a tradeoff between balancing efficiency and speed. This equalizer has two modes: pack-to-pack-group and pack-to-any-pack (P2PG&AP) mode and direct-pack-to-pack (DP2P) mode. In P2PG&AP mode, this equalizer can realize the full-switching-cycle (FSC) equalization through three balancing channels, and transfer energy from any pack to both the whole group and any pack inside the group. In addition, it can effectively clamp the transformer-induced voltage using a secondary side two-transistor magnetic reset structure (STMR) and reduce the total turns of transformer coil from 70 to 50 turns via a secondary side boost converter (SBC). In DP2P mode, this equalizer can realize zero voltage gap (ZVG) equalization. A prototype was tested at different switching frequencies and LC values to validate the theoretical analysis and optimize the bimodal hybrid operation. Experiment results including higher than 89.66% efficiency and minute-level balancing time under different pack voltage distributions show that the proposed topology demonstrates excellent balancing performance. [ABSTRACT FROM AUTHOR]

In recent years, convolution operations often consume a lot of time and energy in deep learning algorithms, and convolution is usually used to remove noise or extract the edges of an image. However, under data-intensive conditions, frequent operations of the above algorithms will cause a significant memory/communication burden to the computing system. This paper proposes a circuit based on spin memristor cross array to solve the problems mentioned above. First, a logic switch based on spin memristors is proposed, which realizes the control of the memristor cross array. Secondly, a new type of spin memristor cross array and peripheral circuits is proposed, which realizes the multiplication and addition operation in the convolution operation and significantly alleviates the computational memory bottleneck. At last, the color image filtering and edge extraction simulation are carried out. By calculating the peak signal-to-noise ratio (PSNR) and structural similarity (SSIM) of the image result, the processing effects of different operators are compared, and the correctness of the circuit is verified. [ABSTRACT FROM AUTHOR]

Active battery equalization and passive battery equalization are two important methods which can solve the inconsistency of battery cells in lithium battery groups. In this paper, a new hybrid battery equalization strategy combinfigureing the active equalizing method with a passive equalizing method is proposed. Among them, the implementation of the active equalizing method uses the bidirectional Flyback converter and Forward converter. This hybrid equalizing strategy adopts the concept of hierarchical equilibrium: it can be divided into two layers, the top layer is the equalization between groups, and the bottom layer is the equalization of group. There are three active equilibrium strategies and one passive equilibrium strategy. For verification purposes, a series of experiments were conducted in MATLAB 2018b/Simulink platform. The simulation and experiment results show that this hybrid battery equalizing method is efficient and feasible. [ABSTRACT FROM AUTHOR]

Effective traffic sign recognition algorithms can assist drivers or automatic driving systems in detecting and recognizing traffic signs in real-time. This paper proposes a multiscale recognition method for traffic signs based on the Gaussian Mixture Model (GMM) and Category Quality Focal Loss (CQFL) to enhance recognition speed and recognition accuracy. Specifically, GMM is utilized to cluster the prior anchors, which are in favor of reducing the clustering error. Meanwhile, considering the most common issue in supervised learning (i.e., the imbalance of data set categories), the category proportion factor is introduced into Quality Focal Loss, which is referred to as CQFL. Furthermore, a five-scale recognition network with a prior anchor allocation strategy is designed for small target objects i.e., traffic sign recognition. Combining five existing tricks, the best speed and accuracy tradeoff on our data set (40.1% mAP and 15 FPS on a single 1080Ti GPU), can be achieved. The experimental results demonstrate that the proposed method is superior to the existing mainstream algorithms, in terms of recognition accuracy and recognition speed. [ABSTRACT FROM AUTHOR]

Although correlation filter-based trackers (CFTs) have made great achievements on both robustness and accuracy, the performance of trackers can still be improved, because most of the existing trackers use either a sole filter template or fixed features fusion weight to represent a target. Herein, a real-time dual-template CFT for various challenge scenarios is proposed in this work. First, the color histograms, histogram of oriented gradient (HOG), and color naming (CN) features are extracted from the target image patch. Then, the dual-template is utilized based on the target response confidence. Meanwhile, in order to solve the various appearance variations in complicated challenge scenarios, the schemes of discriminative appearance model, multi-peaks target re-detection, and scale adaptive are integrated into the proposed tracker. Furthermore, the problem that the filter model may drift or even corrupt is solved by using high confidence template updating technique. In the experiment, 27 existing competitors, including 16 handcrafted features-based trackers (HFTs) and 11 deep features-based trackers (DFTs), are introduced for the comprehensive contrastive analysis on four benchmark databases. The experimental results demonstrate that the proposed tracker performs favorably against state-of-the-art HFTs and is comparable with the DFTs. [ABSTRACT FROM AUTHOR]

A memristor is a nanoscale electronic element that displays a threshold property, non-volatility, and variable conductivity. Its composite circuits are promising for the implementation of intelligence computation, especially for logic operations. In this paper, a flexible logic circuit composed of a spintronic memristor and complementary metal-oxide-semiconductor (CMOS) switches is proposed for the implementation of the basic unbalanced ternary logic gates, including the NAND, NOR, AND, and OR gates. Meanwhile, due to the participation of the memristor and CMOS, the proposed circuit has advantages in terms of non-volatility and load capacity. Furthermore, the input and output of the proposed logic are both constant voltages without signal degradation. All these three merits make the proposed circuit capable of realizing the cascaded logic functions. In order to demonstrate the validity and effectiveness of the entire work, series circuit simulations were carried out. The experimental results indicated that the proposed logic circuit has the potential to realize almost all basic ternary logic gates, and even some more complicated cascaded logic functions with a compact circuit construction, high efficiency, and good robustness. [ABSTRACT FROM AUTHOR]