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Current–voltage characteristic curves of NFinFET are presented and fitted with modified current–voltage (I-V) formulas, where the modified term in the triode region is demonstrated to be indispensable. In the as-known I-V formula, important parameters need to be determined to make both the measured data and the fitting data as close as possible. These parameters include kN (associated with the sizes of the transistor and mobility), λ (associated with early voltage), and Vth (the threshold voltage). The differences between the measured data and the fitting data vary with the applied source–drain bias, proving that the mobility of the carriers is not consistently constant. On the other hand, a modified formula, called the kink effect factor, is negatively or positively added, simulating solitary heat waves or lattice vibration, which disturb the propagation of carriers and thus influence the source–drain current (IDS). The new statistical standard deviations (δ) are then found to be effectively suppressed as the kink effect is taken into account. [ABSTRACT FROM AUTHOR]

In this study, we present some design suggestions for all-polymer solar cells by utilizing device simulation. The polymer solar cell under investigation is formed by a photoactive film of a blend comprising PBDB-T as a polymer donor and PZT as a polymerized small molecule acceptor. The initial cell is based on a fabricated cell whose structure is ITO/PEDOT:PSS/PBDB-T:PZT/PFN-Br/Ag, which has a power conversion efficiency (PCE) of about 14.9%. A calibration procedure is then performed by comparing the simulation results with experimental data to confirm the simulation models, and the material parameters, implemented in the SCAPS (Solar Cell Capacitance Simulator) simulator. To boost the open circuit voltage, we investigate a group of hole transport layer (HTL) materials. An HTL of CuI or P3HT, that may replace the PEDOT:PSS, results in a PCE of higher than 20%. However, this enhanced efficiency results in a minor S-shape curve in the current density-voltage (J-V) characteristic. So, to suppress the possibility of the appearance of an S-curve, we propose a double HTL structure, for which the simulation shows a higher PCE with a suppressed kink phenomenon due to the proper band alignment. Moreover, the designed cell is investigated when subjected to a low light intensity, and the cell shows a good performance, signifying the cell's suitability for indoor applications. The results of this simulation study can add to the potential development of highly efficient all-polymer solar cells. [ABSTRACT FROM AUTHOR]

The raised source/drain (RSD) structure is one of thin film transistor designs that is often used to improve device characteristics. Many studies have mentioned that the high impact ionization rate occurring at a drain side can be reduced, owing to a raised source/drain area that can disperse the drain electric field. In this study, we will discuss how the electric field at the drain side of an RSD device is reduced by a vertical lightly doped drain (LDD) scheme rather than a RSD structure. We used different raised source/drain forms to simulate the drain side electric field for each device, as well as their output characteristics, using Integrated Systems Engineering (ISE-TCAD) simulators. Different source and drain thicknesses and doping profiles were applied to verify the RSD mechanism. We found that the electric fields of a traditional device and uniform doping RSD structures are almost the same (~2.9 × 105 V/cm). The maximum drain electric field could be reduced to ~2 × 105 V/cm if a vertical lightly doped drain RSD scheme was adopted. A pure raised source/drain structure did not benefit the device characteristics if a vertical lightly doped drain design was not included in the raised source/drain areas. [ABSTRACT FROM AUTHOR]

Low power consumption has become one of the major requirements for most microelectronic devices and systems. Increasing power dissipation may lead to decreasing system efficiency and lifetime. The BULK metal oxide semiconductor field-effect transistor (MOSFET) has relatively high power dissipation and low frequency response due to its internal capacitances. Although the silicon-on-insulator (SOI) MOSFET was introduced to resolve these limitations, other challenges were introduced including the kink effect in the current-voltage characteristics. The selective buried oxide (SELBOX) MOSFET was then suggested to resolve the problem of the kink effect. The authors have previously investigated and reported the characteristics of the SELBOX structure in terms of kink effect, frequency, thermal and static power characteristics. In this paper, we continue our investigation by presenting the dynamic power characteristics of the SELBOX structure and compare that with the BULK and SOI structures. The simulated fabrication of the three devices was conducted using Silvaco TCAD tools in 90 nm complementary metal oxide semiconductor (CMOS) technology. Simulation results show that the average dynamic power dissipation of the CMOS BULK, SOI and SELBOX are compatible at high frequencies with approximately 54.5 µW. At low frequencies, the SOI and SELBOX showed comparable dynamic power dissipation but with lower values than the BULK structure. The difference in power dissipation between the SELBOX and BULK is in the order of nano watts. This power difference becomes significant at the chip level. For instance, at 1 MHz, SOI and SELBOX exhibit an average dynamic power consumption of 0.0026 µW less than that of the BULK structure. This value cannot be ignored when a chip operates using thousands or millions of SOI or SELBOX MOSFETs. [ABSTRACT FROM AUTHOR]

In this study, a novel low impact ionization rate (low-IIR) poly-Si thin film transistor featuring a current and electric field split (CES) structure with bottom field plate (BFP) and partial thicker channel raised source/drain (RSD) designs is proposed and demonstrated. The bottom field plate design can allure the electron and alter the electron current path to evade the high electric field area and therefore reduce the device IIR and suppress the kink effect. A two-dimensional device simulator was applied to describe and compare the current path, electric field magnitude distributions, and IIR of the proposed structure and conventional devices. In addition, the advantages of a partial thicker channel RSD design are present, and the leakage current of CES-thin-film transistor (TFT) can be reduced and the ON/OFF current ratio be improved, owing to a smaller drain electric field. [ABSTRACT FROM AUTHOR]

In this paper, the effect of electron irradiation fluence on direct current (DC) and radio frequency (RF) of InP-based high electron mobility transistors (HEMTs) was investigated comprehensively. The devices were exposed to a 1 MeV electron beam with varied irradiation fluences from 1 × 1014 cm−2, 1 × 1015 cm−2, to 1 × 1016 cm−2. Both the channel current and transconductance dramatically decreased as the irradiation fluence rose up to 1 × 1016 cm−2, whereas the specific channel on-resistance (Ron) exhibited an apparent increasing trend. These changes could be responsible for the reduction of mobility in the channel by the irradiation-induced trap charges. However, the kink effect became weaker with the increase of the electron fluence. Additionally, the current gain cut-off frequency (fT) and maximum oscillation frequency (fmax) demonstrated a slightly downward trend as the irradiation fluence rose up to 1 × 1016 cm−2. The degradation of frequency properties was mainly due to the increase of gate-drain capacitance (CGD) and the ratio of gate-drain capacitance and gate-source capacitance (CGD/CGS). Moreover, the increase of Ron may be another important factor for fmax reduction. [ABSTRACT FROM AUTHOR]

This paper presents the effects of optical radiation on the behavior of two scaled-gate aluminum gallium nitride/gallium nitride (AlGaN/GaN) high electron mobility transistors (HEMTs). The tested devices, having a gate width of 100 and 200 µm and a gate length of 0.25 µm, were exposed to a laser beam with a wavelength of 404 nm (blue-ray) in order to investigate the main optical effects on the DC characteristics. Owing to the threshold shift and the charge generation, a marked increase of the gate and drain current was noticed. The occurrence of the kink effect in the absence of light exposure was identified, and a hypothesis about its origin is provided. The obtained results agree with the analysis previously carried out on gallium arsenide (GaAs)-based devices. [ABSTRACT FROM AUTHOR]

A current improved and electric field reduced double-gate (DG) polycrystalline silicon thin-film transistor with two-step source/drain (DGTSD-TFT) design is proposed and demonstrated in this study. The two-step source/drain (TSD) design, which consists of a raised source/drain (RSD) area together with a partial gate overlapped lightly doped drain (P-GOLDD) structure, can lower the device drain electric field (DEF) to reveal a better device performance. Comparisons have been made with respect to a traditional single top gate (STG) device. The operation current of the proposed DGTSD-TFT is almost twice as large as that of the STG structure. The OFF-state leakage current and kink effect, as well as the ON/OFF current ratio for this double-gate and two-step source/drain structure, are also improved simultaneously because of a reduced DEF. A hot carrier stress test reveals that that two-step source/drain structure can achieve more stable device characteristics than the traditional device. [ABSTRACT FROM AUTHOR]