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Time-dependent second-harmonic generation (TD-SHG) is an emerging sensitive and fast method to qualitatively evaluate the interface quality of the oxide/Si heterostructures, which is closely related to the interfacial electric field. Here, the TD-SHG is used to explore the interface quality of atomic layer deposited HfO2 films on Si substrates. The critical SHG parameters, such as the initial SHG signal and characteristic time constant, are compared with the fixed charge density ( Q o x ) and the interface state density ( D i t ) extracted from the conventional electrical characterization method. It reveals that the initial SHG signal linearly decreases with the increase in Q o x , while D i t is linearly correlated to the characteristic time constant. It verifies that the TD-SHG is a sensitive and fast method, as well as simple and noncontact, for evaluating the interface quality of oxide/Si heterostructures, which may facilitate the in-line semiconductor test. [ABSTRACT FROM AUTHOR]

Oxygen post annealing is a promising method for improving the quality of the SiC metal oxide semiconductor (MOS) interface without the introduction of foreign atoms. In addition, a low oxygen partial pressure annealing atmosphere would prevent the additional oxidation of SiC, inhibiting the generation of new defects. This work focuses on the effect and mechanism of low oxygen partial pressure annealing at different temperatures (900–1250 °C) in the SiO2/SiC stack. N2 was used as a protective gas to achieve the low oxygen partial pressure annealing atmosphere. X-ray photoelectron spectroscopy (XPS) characterization was carried out to confirm that there are no N atoms at or near the interface. Based on the reduction in interface trap density (Dit) and border trap density (Nbt), low oxygen partial pressure annealing is proven to be an effective method in improving the interface quality. Vacuum annealing results and time of flight secondary ion mass spectrometry (ToF-SIMS) results reveal that the oxygen vacancy (V[O]) filling near the interface is the dominant annealing mechanism. The V[O] near the interface is filled more by O2 in the annealing atmosphere with the increase in temperature. [ABSTRACT FROM AUTHOR]

In this paper, the effect of atomic layer deposition (ALD)-derived Al2O3 passivation layers and annealing temperatures on the interfacial chemistry and transport properties of sputtering-deposited Er2O3 high-k gate dielectrics on Si substrate has been investigated. X-ray photoelectron spectroscopy (XPS) analyses have showed that the ALD-derived Al2O3 passivation layer remarkably prevents the formation of the low-k hydroxides generated by moisture absorption of the gate oxide and greatly optimizes the gate dielectric properties. Electrical performance measurements of metal oxide semiconductor (MOS) capacitors with different gate stack order have revealed that the lowest leakage current density of 4.57 × 10−9 A/cm2 and the smallest interfacial density of states (Dit) of 2.38 × 1012 cm−2 eV−1 have been achieved in the Al2O3/Er2O3/Si MOS capacitor, which can be attributed to the optimized interface chemistry. Further electrical measurements of annealed Al2O3/Er2O3/Si gate stacks at 450 °C have demonstrated superior dielectric properties with a leakage current density of 1.38 × 10−9 A/cm2. At the same, the leakage current conduction mechanism of MOS devices under various stack structures is systematically investigated. [ABSTRACT FROM AUTHOR]

In this paper, the effect of atomic layer deposition-derived laminated interlayer on the interface chemistry and transport characteristics of sputtering-deposited Sm2O3/InP gate stacks have been investigated systematically. Based on X-ray photoelectron spectroscopy (XPS) measurements, it can be noted that ALD-derived Al2O3 interface passivation layer significantly prevents the appearance of substrate diffusion oxides and substantially optimizes gate dielectric performance. The leakage current experimental results confirm that the Sm2O3/Al2O3/InP stacked gate dielectric structure exhibits a lower leakage current density than the other samples, reaching a value of 2.87 × 10−6 A/cm2. In addition, conductivity analysis shows that high-quality metal oxide semiconductor capacitors based on Sm2O3/Al2O3/InP gate stacks have the lowest interfacial density of states (Dit) value of 1.05 × 1013 cm−2 eV−1. The conduction mechanisms of the InP-based MOS capacitors at low temperatures are not yet known, and to further explore the electron transport in InP-based MOS capacitors with different stacked gate dielectric structures, we placed samples for leakage current measurements at low varying temperatures (77–227 K). Based on the measurement results, Sm2O3/Al2O3/InP stacked gate dielectric is a promising candidate for InP-based metal oxide semiconductor field-effect-transistor devices (MOSFET) in the future. [ABSTRACT FROM AUTHOR]

The interface passivation of the HfO2/Si0.7Ge0.3 stack is systematically investigated based on low-temperature ozone oxidation and Si-cap methods. Compared with the Al2O3/Si0.7Ge0.3 stack, the dispersive feature and interface state density (Dit) of the HfO2/Si0.7Ge0.3 stack MOS (Metal-Oxide-Semiconductor) capacitor under ozone direct oxidation (pre-O sample) increases obviously. This is because the tiny amounts of GeOx in the formed interlayer (IL) oxide layer are more likely to diffuse into HfO2 and cause the HfO2/Si0.7Ge0.3 interface to deteriorate. Moreover, a post-HfO2-deposition (post-O) ozone indirect oxidation is proposed for the HfO2/Si0.7Ge0.3 stack; it is found that compared with pre-O sample, the Dit of the post-O sample decreases by about 50% due to less GeOx available in the IL layer. This is because the amount of oxygen atoms reaching the interface of HfO2/Si0.7Ge0.3 decreases and the thickness of IL in the post-O sample also decreases. To further reduce the Dit of the HfO2/Si0.7Ge0.3 interface, a Si-cap passivation with the optimal thickness of 1 nm is developed and an excellent HfO2/Si0.7Ge0.3 interface with Dit of 1.53 × 1011 eV−1cm−2 @ E−Ev = 0.36 eV is attained. After detailed analysis of the chemical structure of the HfO2/IL/Si-cap/Si0.7Ge0.3 using X-ray photoelectron spectroscopy (XPS), it is confirmed that the excellent HfO2/Si0.7Ge0.3 interface is realized by preventing the formation of Hf-silicate/Hf-germanate and Si oxide originating from the reaction between HfO2 and Si0.7Ge0.3 substrate. [ABSTRACT FROM AUTHOR]

AlGaN/GaN metal-insulator-semiconductor high-electron-mobility transistors (MISHEMT) with a low-temperature epitaxy (LTE)-grown single crystalline AlN gate dielectric were demonstrated for the first time and the post-gate annealing effects at 400 °C were studied. The as-deposited LTE-AlN MISHEMT showed a maximum drain current (IDmax) of 708 mA/mm at a gate bias of 4 V and a maximum extrinsic transconductance (gmmax) of 129 mS/mm. The 400 °C annealed MISHEMT exhibited an increase of 15% in gmmax, an order of magnitude reduction in reverse gate leakage and about a 3% suppression of drain current (ID) collapse. The increase of gmmax by post-gate annealing is consistent with the increase of 2DEG mobility. The suppression of ID collapse and the reduction of gate leakage current is attributed to the reduction of interface state density (5.0 × 1011 cm−2eV−1) between the AlN/GaN interface after post-gate annealing at 400 °C. This study demonstrates that LTE grown AlN is a promising alternate material as gate dielectric for GaN-based MISHEMT application. [ABSTRACT FROM AUTHOR]