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In this paper, we design and implement a firmware for portable PCR devices that is controlled by a smart phone. The firmware has the host-local structure in which the firmware receives operation commands from the smart phone and sends operation results to the smart phone through Bluetooth communication. The firmware is designed to accommodate unstable wireless communication of Bluetooth. We implement a low-cost small PCR device with the proposed firmware on microchip PIC18F4550, and verify that the implemented PCR device significantly reduces volume size of existing commercial PCR devices with a similar performance.

In this paper, we propose techniques that reduce the MAC overhead in IEEE 802.11-based wireless networks. As the channel bit rate increases, MAC overhead becomes a major source of throughput degradation. This is due to the fact that the MAC overhead is rate-independent; it is fixed regardless of the data rate. Rate-independent overhead can be reduced by dividing a high-rate wideband channel into multiple low-rate narrow channels, and send data on these narrow channels simultaneously using multiple or compound radios. In this environment with multiple narrow channels, we propose two techniques that further reduce MAC overhead and thus improve resource efficiency. First, channel contention is done only on one of the narrow channels, called the contention channel. The other channels are accessed based on the status of the contention channel, without contention. This technique significantly improves network throughput, but has a problem in which if a collision occurs on the contention channel, collisions can also occur on other channels. To avoid this phenomenon, we propose the second technique in which a node observing collision notifies the senders that cause collision, so that they do not access other channels simultaneously. Extensive simulation results show that the proposed techniques improve network throughput by a considerable amount.

Manycore processor architectures are currently very widely used in almost all computer systems. Furthermore, many computer science department have started to teach parallel programming on manycore system platforms. To best understand the parallel programming on those manycore processors, the classes on manycore processor architecture also have to be provided. However, most current undergraduate computer architecture classes have not yet provided. In this paper, we have design a manycore processor design using a conventional MIPS processor design that is considered as a standard processor architecture model in a traditional undergraduate computer architecture class. Synthesize manycore processor models are developed in 850 lines of Verilog-HDL together with simple parallel applications so students can understand the entire manycore processor design and can learn the basics of the manycore system including underlying communication architecture.