1. A CMOS reduced-area SRAM cell
- Author
-
Evert Seevinck, Trudi-Heleen Joubert, and M. du Plessis
- Subjects
Engineering ,business.industry ,Transistor ,Sram cell ,Hardware_PERFORMANCEANDRELIABILITY ,Integrated circuit layout ,law.invention ,Threshold voltage ,CMOS ,law ,Memory architecture ,Hardware_INTEGRATEDCIRCUITS ,Electronic engineering ,Static random-access memory ,Routing (electronic design automation) ,business - Abstract
In CMOS, an SRAM cell containing six transistors and five routing wires is generally used. If a smaller number of transistors and/or fewer connection lines were possible, the packing density of SRAM chips may be improved. In this paper, a four-transistor SRAM cell for implementation in a standard digital CMOS process is proposed. The implementation of the smallest area cell in a 1.2 /spl mu/m n-well CMOS process shows successful cell operation. Two memory block architectures are also discussed, as well as the specific cell configurations for correct operation. Depending on the memory block architecture, the four-transistor cell area reduction, when compared to a six-transistor cell, is either 14.7% or 37.3%.
- Published
- 2002