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Advancements in AI led to the emergence of in-memory-computing architectures as a promising solution for the associated computing and memory challenges. This study introduces a novel in-memory-computing (IMC) crossbar macro utilizing a multi-level FeFET cell for multi-bit multiply and accumulate (MAC) operations. The proposed 1FeFET-1R cell design stores multi-bit information while minimizing device variabil21 ity effects on accuracy. Experimental validation was performed using 28 nm HKMG technology-based ferroelectric field-effect transistor (FeFET) devices. Unlike tradi23 tional resistive memory-based analog computing, our approach leverages the electrical characteristics of stored data within the memory cell to derive MAC operation results encoded in activation time and accumulated current. Remarkably, our design achieves 96.6%accuracy for handwriting recognition and 91.5%accuracy for image classification without extra training. Furthermore, it demonstrates exceptional performance, achiev28 ing 885.4 TOPS/W–nearly double that of existing designs. This study represents the first successful implementation of an in-memory macro using a multi-state FeFET cell for complete MAC operations, preserving crossbar density without additional struc31 tural overhead.

This work demonstrates an innovative methodology that utilizes laser irradiation to deduce the age of SRAMs within an Integrated Circuit (IC). Our proposed approach broadens the horizon for effective counterfeit IC detection– with the supplemental capability of approximating the age of ICs. This is momentous for sectors with highly prioritized safety standards, such as automotives. Our analysis is initiated by validating the nMOS and pMOS transistors within a 6-T SRAM cell against measurements of 22 nm FDSOI industrial transistors. Using accurate multi-physics Technology Computer-Aided Design (TCAD) simulations, we investigate the minimum laser energy at which bit-flip occurs in SRAM cells that are fresh and aged to varying extents. TCAD-based simulations capture the complex interactions of the underlying transistor physics, accounting for 1) aging-induced defects and 2) the electron-hole pairs generated by incident laser photons. Aging phenomena such as Bias Temperature Instability (BTI) and Hot-carrier Injection (HCI) manifest themselves as a shift in transistor electrical characteristics like threshold voltage (ΔVth) and carrier mobility (μ). As a result, SRAM reliability is seriously diminished. Simultaneously, laser irradiation creates electron-hole pairs that temporally decrease the transistor ON current. The combined effect of these processes further degrades SRAM reliability and considerably heightens the probability of bit-flip occurrence. Therefore, to test for bit-flip susceptibility, laser characteristics can be feasibly fine-tuned in accordance to the relation between 1) aging-induced ΔVth and 2) the minimum laser energy required to cause a bit-flip. Hence, our proposed methodology emerges as a facile yet effective solution to the problem of widespread counterfeit proliferation that is further aggravated by the current chip famine. This work presents the first step toward realizing a counterfeit detection technique that merely entails shining laser light on an IC and calculating the resulting SRAM bit-flip probability. Accordingly, the newness of an IC can be ascertained, else, if it is used (as is the case of a counterfeit), its operational lifetime can be estimated.