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This paper presents up-to-date side-channel attacks and their countermeasures. A classification of side-channel attacks and countermeasures is done and how to design a model of side-channel attack is presented. A novel transistor-level countermeasure approach, three-phase dual-rail pre-charge logic (TDPL), against side-channel attacks based on analysis of crypto core's leakage currents is explained. Algorithms and models to predict the input vector for maximum and minimum leakage current in CMOS and TDPL gates are reviewed. Extensive transistor level simulations on basic gates implemented in 65 nm CMOS technology are presented and a methodology to analyze this data and compare CMOS vs. TDPL as a possible countermeasures. The results of this study show that leakage current can be easily exploited as a side channel by an attacker to extract information about the secret key in cryptographic hardware in CMOS crypto-design, while TDPL can be a reliable countermeasure to use in future design of smart cards. [ABSTRACT FROM AUTHOR]