38 results on '"Chen, Yijian"'
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2. A paradigm shift in patterning foundation from frequency multiplication to edge-placement accuracy: a novel processing solution by selective etching and alternating-material self-aligned multiple patterning
3. Structural design, layout analysis and routing strategy for constructing IC standard cells using emerging 3D vertical MOSFETs
4. A comparative study on the yield performance of via landing and direct stitching processes for 2D pattern connection
5. Layout decomposition and synthesis for a modular technology to solve the edge-placement challenges by combining selective etching, direct stitching, and alternating-material self-aligned multiple patterning processes
6. Impacts of process variability of alternating-material self-aligned multiple patterning on SRAM circuit performance
7. Statistical modeling of SRAM yield performance and circuit variability
8. Breaking through 1D layout limitations and regaining 2D design freedom part II: stitching yield modeling and optimization
9. Breaking through 1D layout limitations and regaining 2D design freedom Part I: 2D layout decomposition and stitching techniques for hybrid optical and self-aligned multiple patterning
10. A compact model to predict pillar-edge-roughness effects on 3D vertical nanowire MOSFETs using the perturbation method
11. Understanding the critical challenges of self-aligned octuple patterning
12. A generalized edge-placement yield model for the cut-hole patterning process
13. A generalized model to predict fin-width roughness induced FinFET device variability using the boundary perturbation method
14. A layout decomposition algorithm for self-aligned multiple patterning
15. A frequency multiplication technique based on EUV near-field imaging
16. Benchmarking process integration and layout decomposition of directed self-assembly and self-aligned multiple patterning techniques
17. A comparative study of self-aligned quadruple and sextuple patterning techniques for sub-15nm IC scaling
18. SRAM circuit performance in the presence of process variability of self-aligned multiple patterning
19. Cut-process overlay yield model for self-aligned multiple patterning and a misalignment correction technique based on dry etching
20. Compact modeling of fin-width roughness induced FinFET device variability using the perturbation method
21. Process characteristics and layout decomposition of self-aligned sextuple patterning
22. Mask strategy and layout decomposition for self-aligned quadruple patterning
23. Overlay, decomposition and synthesis methodology for hybrid self-aligned triple and negative-tone double patterning
24. Mandrel and spacer engineering based self-aligned triple patterning
25. Intra-cell process variability and compact modeling of LWR effects: from self-aligned multiple patterning to multiple-gate MOSFETs
26. Maskless EUV lithography: an already difficult technology made even more complicated?
27. Technological merits, process complexity, and cost analysis of self-aligned multiple patterning
28. Recessive self-aligned double patterning with gap-fill technology
29. Spatial frequency multiplication techniques towards half-pitch 10nm patterning
30. Self-aligned triple patterning for continuous IC scaling to half-pitch 15nm
31. Mandrel-based patterning: density multiplication techniques for 15nm nodes
32. Sidewall spacer quadruple patterning for 15nm half-pitch
33. Sub-20 nm trench patterning with a hybrid chemical shrink and SAFIER process
34. A predictive method to forecast spatial variability of stochastic processes for deep nanoscale semiconductor manufacturing
35. The effects of wafer-scan induced image blur on CD control, image slope, and process window in maskless lithography
36. Design and fabrication of tilting and piston micromirrors for maskless lithography
37. Optical analysis of mirror-based pattern generation
38. Control and shape design of an electrically damped comb drive for digital switches
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