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Fabrication processes that microelectronic developed for Integrated circuit (IC) technologies for decades, do not meet the new emerging structuration’s requirements, in particular non-IC related technologies one, such as MEMS/NEMS, Micro-Fluidics, photovoltaics, lenses. Actually complex 3D structuration requires complex lithography patterning approaches such as gray-scale electron beam lithography, laser ablation, focused ion beam lithography, two photon polymerization. It is now challenging to find cheaper and easiest technique to achieve 3D structures. In this work, we propose a straightforward process to realize 3D structuration, intended for silicon based materials (Si, SiN, SiOCH). This structuration technique is based on nano-imprint lithography (NIL), ion implantation and selective wet etching. In a first step a pattern is performed by lithography on a substrate, then ion implantation is realized through a resist mask in order to create localized modifications in the material, thus the pattern is transferred into the subjacent layer. Finally, after the resist stripping, a selective wet etching is carried out to remove selectively the modified material regarding the non-modified one. In this paper, we will first present results achieved with simple 2D line array pattern processed either on Silicon or SiOCH samples. This step have been carried out to demonstrate the feasibility of this new structuration process. SEM pictures reveals that “infinite” selectivity between the implanted areas versus the non-implanted one could be achieved. We will show that a key combination between the type of implanted ion species and wet etching chemistries is required to obtain such results. The mechanisms understanding involved during both implantation and wet etching processes will also be presented through fine characterizations with Photoluminescence, Raman and Secondary Ion Mass Spectrometry (SIMS) for silicon samples, and ellipso-porosimetry and Fourier Transform InfraRed spectroscopy (FTIR) for SiOCH samples. Finally the benefit of this new patterning approach will be presented on 3D patterns structures.

In this paper, we communicate on the design, fabrication, and testing of optical modulators for Silicon-based photonic integrated circuits (Si-PICs) in the O-band (1.31 μm), targeting the 100GBASE-LR4 norm (4 wavelengths at 25 Gbit/s). The modulators have been conceived to be later coupled with hybrid-III-V/Si lasers as well as echelle grating multiplexer, to create a hetero-integrated optical transmitter on a silicon-on-insulator (SOI) platform. The devices are based on a Mach-Zehnder Interferometer (MZI) architecture, where a p-n junction is implanted to provide optical modulation through carrier depletion. A detailed study focusing on the best doping scheme for the junction, aimed at optimizing the overall transmitter performance and power-efficiency is presented. In detail, the trade-off between low optical losses and high modulation efficiency is tackled, with a targeted CMOS-compatible voltage drive of 2.5 V. Process simulations of the junction are realized for the doping profile optimization. Modulators of different lengths are also investigated to study the compromise between extinction ratio, insertion losses and bandwidth. Furthermore, coplanar-strip (SGS) travelling-wave electrodes are designed to maximize the bandwidth, to reach the targeted bit rate of 25 Gbit/s. Measurements show modulation efficiencies up to 19 °/mm (or 2.4 V.cm) for a 2.5 V input voltage, with doping-related losses below 1 dB/mm, in line with theoretical estimates, and well-suited to enhance the Si-PIC transmission and power-efficiency. Finally, an electro-optical (EO) bandwidth at 1.25 V bias is measured above 28 GHz.