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As the scaling down of design rule for high density memory device continues, the contact hole size shrinkage becomes one of the major challenges to patterning. Many shrinkage approaches have been introduced after litho. process, such as chemical shrink, PR reflow, RIE shrink, etc. However, CD uniformity control for these shrink processes is critical, and minimum pitch size is still dominated by the resolution limitation of lithography tools. In this paper, we adopt SADP (self-aligned double patterning) process combined with additional non-critical mask step to form 32nm hp elliptical single row dense and isolated contact holes. The CD uniformity is well controlled by SADP process, and chip size reduction is achievable by this high-density single row layout compared with interlace contact hole design. We also compared this new approach with chemical shrink process, and both the CD uniformity and resolution limit are improved. With optimized step-by-step etch process, we have successfully demonstrated the contact hole patterns on full-structure substrate. For the future application toward sub-2x nm node, this approach is also expectable with mature SADP process.

Resist supplier has successfully demonstrated applying negative tone resist into ArF lithography. It is capable of achieving 50nm dense line and 0.21um DOF and 4.6nm global CDU are achieved on DRAM capacitor process. It revealed strong relation to development parameter setting. Furthermore, specific pattern formation considering optical items, ex: OPE, NRF (non-resolution feature) and interaction between double exposure have also been analyzed and difficulties of generating a specific pattern with negative tone resist double exposure have been figured out.

When the feature size keep shrinking to 4Xnm, ArF lithography has already proceed to immersion process and became mature enough. There is an important factor that will obviously influence photo process window in the initial phase development is the optical reflection from imperfect substrate design. From previous experience, reflection would be optimized to fine level by adjusting TARC (Top Anti-Reflection Coating) or BARC (Bottom Anti-Reflection Coating) thickness through index of reflectivity. However, actual criteria of reflectivity for various ArF lithography process are unlikely the same, e.g. different system type (wet/dry), node (feature size), illumination type, or even substrate effect, and also need to be examined to retain a decent process window. In this paper, experimental result of various abovementioned ArF process have been compared with reflectivity index from prolith simulation engine, and distinctly clarified criteria of reflectivity for each case. Furthermore, effects of reflection to several optics caused patterning-related results, e.g. IDB (Iso-Dense Bias), OPC (Optical Proximate Correction) accuracy, will also be discussed. The result also shows severe criterion of reflection is requested as feature size getting smaller to 4Xnm node, and RET-applied (Resolution Enhancement Technology) process has opposite result on it. From experimental results, IDB has been obviously affected by reflection and become one important factor that influences reflection criterion examination.

As IC manufacturing goes from 45nm to 30nm node half-pitch, the lithography process k1 factor will fall below 0.25 by using water-based ArF-immersion scanner. To bridge the gap between ArF-immersion and next generation lithography, which is not ready yet for production, Double Patterning Technology (DPT) has been evaluated and identified as a promising solution as it utilizes existing equipment and processes. Self Aligned Double Patterning (SADP) has the advantage of dense array definition without overlay issue and is hence useful for memory device; but its characteristic restricts the feasibility of two-dimensional circuit pattern definition on the other hand. This paper describes the ideas of 30nm node NAND FLASH cell circuit critical feature (pickup, gate, contact array) definition by decomposing the target patterns to SADP defined dense array in conjunction with cropping and/or periphery masks steps. The concerns and issues of cropping/periphery mask step process integration as well as SADP alignment algorithm are investigated, and the countermeasures with alternative process schemes and novel frame designs are presented. Finally, simulation prediction has shown that the capability of 30nm NAND FLASH critical features patterning with depth of focus equal to or above 0.15um is expected at each mask step by ArF-dry lithography.

Double patterning technology (DPT) is the best alternative to achieve 3x NAND flash node by 193nm immersion lithography before entering EUV regime. Self-aligned double patterning (SADP) process is one of several DPT approaches, and most likely be introduced into NAND flash manufacture. The typical single exposure process in 40nm node flash will become into multiple exposure job in 32nm node by DPT or SADP, and the overlay control among these multiple exposure will be highly restricted than single exposure process. To reach tight overlay spec. mainly relies on the contribution of alignment system of scanner, but the well alignment mark design with high contrast signal and outstanding sustainability are essential factor as well. Typically, the feature size patterned in SADP around 3x nm that is too narrow to form essential signals that is qualified to be the alignment mark and the overlay mark either. This paper, we will discuss 1. the performance of alignment algorithm on direct alignment and indirect alignment 2. different alignment mark design and 3. film scheme dependence (layer dependence). And experiment result show the new mark design performs sufficient contrast and signal for subsequent layer aligning process.