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In this work, we present the framework surrounding the development of a mmW radar image-based algorithm for wire recognition and classification for rotorcraft operation in degraded visual environments. While a mmW sensor image lacks the optical resolution and perspective of an IR or LIDAR sensor, it currently presents the only true see-through mitigation under the heaviest of degraded vision conditions. Additionally, the mmW sensor produces a high-resolution, radar map that has proven to be exceedingly interpretable, especially to a familiar operator. Seizing on these clear advantages, the mmW radar image-based algorithm is trained and evaluated against independent mmW imagery data collected from a live flight test in a relevant environment. The foundation of our approach is based on image processing and machine learning techniques utilizing radar-based signal properties and sensor and platform information for added robustness. We discuss some of the requirements and practical challenges of a standalone algorithm development, and lastly, present some preliminary examples using existing development tools and discuss the path for continued advancement and evaluation.

The outstanding coding performance of H.264 comes with the cost of significantly higher complexity, making it too complex to be applied widely. This work aims at accelerating the H.264 encoder using joint algorithm/code-level optimization techniques so as to make it feasible to perform real-time encoding on a commercial personal computer. We propose a fast inter-mode decision scheme based on spatio-temporal information of neighboring macroblocks for the algorithm-level optimization. We use a commercial profiling tool to identify most time consuming modules and then apply several code-level optimization techniques, including frame-memory rearrangement, single-instruction-multipledata (SIMD) implementations based on the Intel MMX/SSE2 instruction sets. Search mode reordering and early termination for variable block-size motion estimation, are then applied to speed up these time-critical modules. The simulation results show that our proposed joint optimization H.264 encoder achieves a speed-up factor of up to 18 compared to the reference encoder without introducing serious quality degradation.

In this paper, early-stop and Motion Vector (MV) re-use approaches are proposed for the MPEG-2 to H.264 transcoding to reduce the computation of the variable block-size motion estimation. By combining the two approaches, the number of MV search points is reduced by more than 80% without significantly affecting the video quality. The proposed approaches can also be used in fast variable block-size motion estimation for the H.264 video encoding.

Global motion estimation is a powerful tool used in computer vision and video processing. In this paper, we propose an efficient approach of estimating general global motion parameters from coarsely sampled motion vector fields. The approach is based on gradient descent with outlier rejection. Experimental results show the effectiveness of the method in terms of robustness and accuracy.

In video transcoding, useful coding statistics become available when the input video stream is decoded. It is possible to utilize these statistics to improve the transcoding performance. In this paper we investigate how to use these statistics to perform the picture bit-allocation for transcoding a pre-encoded video bit-stream. We propose a scheme to estimate the complexities of the pictures of the output video using the coding statistics computed from the input video stream. Based on the estimated picture complexity, we present a picture bit-allocation algorithm for the rate-control of the transcoding process. The algorithm is simple to compute, and effectively improves the video quality and reduces the picture quality variations.

We investigate the scenario of using the Automatic Repeat reQuest (ARQ) retransmission scheme for two-way low bit-rate video communications over wireless Rayleigh fading channels. We show that during the retransmissions of error packets, due to the reduced channel throughput, the video encoder buffer may fill-up quickly and cause the TMN8 rate-control algorithm to significantly reduce the bits allocated to each video frame. This results in Peak Signal-to-Noise Ratio (PSNR) degradation and many skipped frames. To reduce the number of frames skipped, in this paper we propose a coding scheme which takes into consideration the effects of the video buffer fill-up, an a priori channel model, the channel feedback information, and hybrid ARQ/FEC. The simulation results indicate that our proposed scheme encode the video sequences with much fewer frame skipping and with higher PSNR compared to H.263 TMN8.

Most previous research efforts on video transcoding have been focused on changing the bit-rate of one pre-encoded bit-stream to another. However, in many applications (e.g. streaming video over a heterogeneous network), it may require to transcode a pre-encoded video bit-stream to multiple bit-streams with different bit-rates and features to support multiple clients with different requirements. In this paper, we discuss the case of point-to-multipoint transcoding. We compare two transcoder architectures in terms of processing speed for H.263 and MPEG-2 transcoding. We show that for point-to-multipoint transcoding, a cascaded video transcoder is more efficient since some parts of the transcoder can be shared by the multiple clients.

For visual communication services to be truly ubiquitous, transmission of video signals over the wireless medium should be feasible with acceptable quality. Wireless transmission characteristics are dominated by channel effects like multipath propagation and Doppler frequency which result in severe error bursts and time-varying signal strengths. Such channel effects pose serious challenges to real-time visual communications systems. In this paper, we describe a software based wireless visual communications simulation platform which can be used to evaluate wireless video performance in real-time. The platform consists of two personal computers serving as hosts. Major components of each PC host include a real-time programmable video codec, a wireless channel simulator, and a network interface for data transport between the two hosts. These three components are interfaced in real-time to show the interaction of various wireless channels and video coding algorithms. The programmable features in the above components give us the flexibility to study various wireless channel effects without physically carrying out these experiments. Physically building such systems can be very time-consuming, costly, and the experiments are only limited in scope.

Multi-point videoconferencing provides the full benefits of teleconference but also incurs more involved technical issues. This paper does a detailed analysis of a continuous presence video bridge using the H.261 video coding standard. We first describe the architecture and the required operations of a coded domain bridge using H.261. We then derive the bounds of the bridge delay and the required buffer size for the implementation of the bridge. The delay and the buffer occupancy of the video bridge depend on the order, complexity, and the bit- distribution of the input video sources. To investigate a typical case, we simulate the delay and the buffer occupancy of a video bridge. We also provide a heuristic method to estimate the delay in a typical case. Several techniques were discussed to minimize the bridge delay and the buffer size. Finally, we simulate an intra slice coding and show that the delay and the buffer size can be reduced significantly using this technique.© (1993) COPYRIGHT SPIE--The International Society for Optical Engineering. Downloading of the abstract is permitted for personal use only.

The Discrete Cosine Transform (DCT) is considered to be the most effective transfonn coding technique for image and video compression. In this paper a new implementation of an experimental prototype multi-function DCT/IDCT (Inverse DCT) chip is reported. The chip is based on a distributed arithmetic architecture. The main features of the chip include: 1) The DCT and the IDCT are integrated in the same chip 2) the chip achieves high accuracy exceeding the stringent requirements of a proposed CCITF standard 3) it achieves a high operating speed of 27 MHz and is thus applicable to a wide-range of real-time image and video applications 4) the internal clock frequency is the same as the pixel rate and 5) with an on-chip zigzag scan converter and an adder/subtractor it is multifunctional and useful in a DPCM configuration. The chip is implemented with standard cells and contains about 156k transistors.© (1990) COPYRIGHT SPIE--The International Society for Optical Engineering. Downloading of the abstract is permitted for personal use only.

In this paper, a VLC decoder IC based on the table-lookup technique is described. In this design, a barrel shifter is employed to shift a number of bits corresponding to the decoded codeword. This parallel approach lowers the hardware speed constraint and reduces the system buffer memory size as well. The barrel shifter in conjunction with a codeword table and a word-length table makes the one-step decoding possible. The table storage required by this approach is the type of associative memory which is most efficiently implemented in Programmable Logic Arrays (PLAs). A Content Addressable Memory (CAM) approach that facilitates programmability is also addressed. Design considerations for multiple code tables and tables containing escape codes are discussed for more general applications of the decoder IC. The important issue of decoder interface circuitry, often ignored by others, is also fully considered. Such circuitry can greatly reduce the system complexity. Finally, the implementation of a mask programmable VLC decoder IC is demonstrated using a silicon compiler. Based on our simulations, the output symbol rate for a VLC decoder with 64 entries is about 30 MHz. This speed is high enough for most real-time applications including CCIR 601 digital video (Y: 13.5 MHz, U and V: 6.75 MHz each).

In this paper, we describe a single chip VLSI implementation of a Motion Compensation algorithm for a very low bit-rate motion video codec. Our design aims at implementing the Block Matching Algorithm (BMA). The novel features of our design are the followings: 1. It has full-search capability. 2. It allows sequential data inputs but performs parallel processing with 100% efficiency. 3. Common buses are used for data transfer. 4. It is a highly modular design and easy to expand. 5. It contains testing circuitry. The design has been laid out. Simulation results show that with the use of double metal 1.2µ CMOS process, the design will be able to run up to 25 MHz. The schematic design for fractional-precision block matching system is also described in this paper.

Among various transform coding techniques for image compression the Discrete Cosine Transform (DCT) is considered to be the most effective method and has been widely used in the laboratory as well as in the market, place. DCT is computationally intensive. For video application at 14.3 MHz sample rate, a direct implementation of a 16x16 DCT requires a throughput, rate of approximately half a billion multiplications per second. In order to reduce the cost of hardware implementation, a single chip DCT implementation is highly desirable. In this paper, the implementation of a 16x16 DCT chip using a concurrent architecture will be presented. The chip is designed for real-time processing of 14.3 MHz sampled video data. It uses row-column decomposition to implement the two-dimensional transform. Distributed arithmetic combined with hit-serial and hit-parallel structures is used to implement the required vector inner products concurrently. Several schemes are utilized to reduce the size of required memory. The resultant circuit only uses memory, shift registers, and adders. No multipliers are required. It achieves high speed performance with a very regular and efficient integrated circuit realization. The chip accepts 0-bit input and produces 14-bit DCT coefficients. 12 bits are maintained after the first one-dimensional transform. The circuit has been laid out using a 2-μm CMOS technology with a symbolic design tool MULGA. The core contains approximately 73,000 transistors in an area of 7.2 x 7.0