31 results on '"Chong, Frederic T."'
Search Results
2. Putting Trojans on the Horns of a Dilemma: Redundancy for Information Theft Detection
3. Using Application Bisection Bandwidth to Guide Tile Size Selection for the Synchroscalar Tile-Based Architecture
4. A Realizable Distributed Ion-Trap Quantum Computer
5. Experiences Using Minos as a Tool for Capturing and Analyzing Novel Worms for Unknown Vulnerabilities
6. Synchroscalar: Initial Lessons in Power-Aware Design of a Tile-Based Embedded Architecture
7. HLSpower: Hybrid Statistical Modeling of the Superscalar Power-Performance Design Space
8. Packaging and multiplexing of hierarchical scalable expanders
9. Power-Aware Resource Allocation for CPU- and Memory-Intense Internet Services
10. Putting Trojans on the Horns of a Dilemma: Redundancy for Information Theft Detection
11. A Realizable Distributed Ion-Trap Quantum Computer
12. Synchroscalar: Initial Lessons in Power-Aware Design of a Tile-Based Embedded Architecture
13. Experiences Using Minos as a Tool for Capturing and Analyzing Novel Worms for Unknown Vulnerabilities
14. HLSpower: Hybrid Statistical Modeling of the Superscalar Power-Performance Design Space
15. Packaging and multiplexing of hierarchical scalable expanders
16. The DIVA Emulator: Accelerating Architecture Studies for PIM-Based Systems
17. Summary of Question/Answer Sessions for Workshop Presentations
18. Software Controlled Reconfigurable On-chip Memory for High Performance Computing
19. Performance/Energy Efficiency of Variable Line-Size Caches for Intelligent Memory Systems
20. Compiler-Directed Cache Line Size Adaptivity ⋆
21. Content-Based Prefetching: Initial Results
22. Exploiting On-chip Memory Bandwidth in the VIRAM Compiler
23. Energy/Performance Design of Memory Hierarchies for Processor-in-Memory Chips⋆
24. SAGE: A New Analysis and Optimization System for FlexRAM Architecture
25. Memory Management in a PIM-Based Architecture
26. Aggressive Memory-Aware Compilation
27. FlexCache: A Framework for Flexible Compiler Generated Data Caching
28. The Characterization of Data Intensive Memory Workloads on Distributed PIM Systems⋆
29. Adaptively Mapping Code in an Intelligent Memory Architecture
30. A 64Mbit Mesochronous Hybrid Wave Pipelined Multibank DRAM Macro
31. Memory System Support for Dynamic Cache Line Assembly
Catalog
Books, media, physical & digital resources
Discovery Service for Jio Institute Digital Library
For full access to our library's resources, please sign in.