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The power consumption of battery powered and energy scavenging devices has become a major design metric for embedded systems. Increasingly complex software applications as well as rising demands in operating times, while having restricted power budgets are main drivers of power-aware system design as well as power management techniques. Within this work, a hardware-accelerated estimation-based power profiling unit delivering real-time power information has been developed. Power consumption feedback to the designer allows for real-time power analysis of embedded systems. Power saving potential as well as power-critical events can be identified in much less time compared to power simulations. Hence, the designer can take countermeasures already at early design stages, which enhances development efficiency and decreases time-to-market. Moreover, this work forms the basis for estimation-based on-chip power management by leveraging the power information for adoptions on system frequency and supply voltage in order to enhance the power efficiency of embedded systems. Power estimation accuracies achieved for a deep sub-micron smart-card controller are above 90% compared to gate-level simulations.

The simplest question in this part is that of the current status regarding the three targets of the Energiewende, as described in the first part. It can essentially be answered on the basis of objective data.

An amplifier receives a signal from an input source and provides a scaled version of the signal to an output device such as an antenna or to another amplifier stage. In small-signal amplifiers, the main factors are usually linearity, gain, and efficiency. For small-signal analysis, the amount of power handling capacity and power efficiency are of little concern. Large-signal devices such as power amplifiers (PAs), on the other hand, primarily provide sufficient power to an output load to drive another device, typically a few watts to tens of watts.

For the purpose of structural enhancement and backwards compatibility, more than two binary signals on one carrier frequency are required to emit. In order to maximize the power efficiency, constant-envelope modulation is adopted. Alt-BOC and ACE-BOC modulations, the constant-envelope modulation that multiplexes four binary spreading codes as two QPSK signals at two different carrier frequencies, are proposed by Galileo and BeiDou respectively. A constraint of these new modulations is that the number of signals to be multiplexed must be no larger than four signal channels. In this paper, a generalized dual-frequency constant-envelope multiplexing technology, named generalized constant envelope BOC (GCE-BOC) modulation, is presented. The modulation can be regarded as the extended form of Alt-BOC and ACE-BOC modulations and provides a solution to dual-frequency constant envelope multiplexing problem for worldwide GNSS.

Biogas is easily transportable, storable and CO2 neutral. The scope of this work is to show the feasibility of H2 production through Auto Thermal Reforming (ATR) of biogas and its utilisation in High Temperature Proton Exchange Membrane Fuel Cell (HT-PEM FC) application. In this study, a fuel cell system was modelled and simulated using MATLAB/Simulink to find the feasibility of biogas reforming for High Temperature Proton Exchange Membrane (HT PEM) Fuel Cell Application. The main criteria considered are high yield of H2 and lowest possible CO. The optimum temperature, Steam to Carbon Ratio (SCR), Air-Fuel Ratio (AFR), and reforming temperature were found out with the help of simulation. A test reference 5 kWth Auto Thermal Reformer (ATR) with Water Gas Shift (WGS) reactor was built according to the simulation guidelines in order to produce H2 to feed a 1 kWel HT-PEM Fuel Cell with anode gas. The reliability and the durability of the system were tested with a start-and-stop strategy and a continuous mode respectively. The electrical efficiency of the whole Fuel Cell system was simulated to around 30 %. The experimental work validated the simulation results within acceptable margins. The experimental study shows that it is not only feasible to produce on-board H2 with biogas but also that the start-and-stop mode of operation does not damage the fuel cell which makes it even suitable for automotive application.

The design of the condensation temperature is crucial to the annual power conversion of the ORC. For an ORC that only generates power, the operating condensation temperature fluctuates greatly in many areas through the year due to the variation of environment temperature.

This paper proposes a scalable and distributed electrical power monitoring system utilizing cloud computing. This system collects power usage at measurement points geographically distributed over different locations, stores data on the cloud and provides a single unified view of power usage through a simple REST API. A system with 620 measurement points covering a server room and a clean room has been successfully installed at our campus, and we have operated it since the third quarter of 2011 to charge electricity bills and evaluate the power efficiency of data processing middleware. We have demonstrated that the proposed system can be smoothly scaled out based on the needs. This result provides an insight that cloud computing makes a power monitoring system elastic and cost-effective.

AltBOC (15, 10) modulation can carry different information on its lower and upper lobes. The two lobes can be received and processed separately as BPSK (10) signal, or coherently processed to achieve better performance. However, AltBOC modulation has lower efficiency and great satellite implementation and receiver processing complexity. TD-AltBOC was proposed to reduce the complexity, and ACED (Asymmetric Constant Envelope Double-sideband) was proposed to improve flexibility of power allocation among the four signals as a cost of complexity increasing further. Nevertheless the correlation power efficiency of these methods is 81.06 %. A novel multiplexing scheme named as CBFH (Coherent Binary Frequency-Hopping) is presented in this paper. The signal generation principle and receiving method are given, and its power spectrum, power efficiency, processing flexibility and complexity are compared with AltBOC, TD-AltBOC and ACED. The Results show that the spectrum of CBFH is similar to AltBOC, TD-AltBOC and ACED. CBFH has the same performance as TD-AltBOC when two-level sub-carrier was adopted; CBFH has the best performance when its complexity as the same as AltBOC or ACED, or CBFH has the lowest complexity when its performance as the same as AltBOC or ACED. CBFH will be a good solution for COMPASS B2 navigation signal.

As threads of execution in a multi-programmed computing environment have different characteristics and hardware resource requirements, heterogeneous multi-core processors can achieve higher performance as well as power efficiency than homogeneous multi-core processors. To fully tap into that potential, OS schedulers need to be heterogeneity-aware, so they can match threads to cores according to characteristics of both. We propose two heterogeneity-aware thread schedulers, PBS and LCSS. PBS makes scheduling based on applications' sensitivity on large cores, and assigns large cores to applications that can achieve better performance gains. LCSS balances the large core resource among all applications. We have implemented these two schedulers in Linux and evaluated their performance with the PARSEC benchmark on different heterogeneous architectures. Overall, PBS outperforms Linux scheduler by 13.3% on average and up to 18%. LCSS achieves a speedup of 5.3% on average and up to 6% over Linux scheduler. Besides, PBS brings good performance with both asymmetric and symmetric workloads, while LCSS is more suitable for scheduling symmetric workloads. In summary, PBS and LCSS provide repeatability of performance measurement and better performance than the Linux OS scheduler.

Power efficient communication in a Wireless Body Area Network (WBAN) is critical for successful system deployment. Stringent constraints of size and weight of sensors significantly limit available sensor power, particularly in the case of implantable sensors. This paper discusses and analyses methods that could be used to improve power efficiency of implantable WBAN systems, with focus on the Wake Up Radio (WUR), which allows power efficient listening of wireless channel. The paper presents analysis of existing hardware and design trade offs in WUR implementation.

In this paper, a novel Low-Voltage, High-Efficiency on-Chip Current Sensing Circuit is designed and realized for the Current Mode Control BUCK DC/DC Converter.Differ from the conventional current-sensing techniques, the proposed circuit utilize the sensing of power MOS turn-on resistance Ron technique which lower the sensing dissipation and improve the power efficiency, meanwhile, the current-sensing circuit without OP amplifier so that it can work at the 2.2V supply voltage. The Chip is simulated and fabricated based on the 0.5μm 2P3M Mixed Signal CMOS process. Test result shows, under heavy load conditions, that efficiency can reach 93%.

Due to growth of energy consumption by HPC servers and data centers many research efforts aim at addressing the problem of energy efficiency. Hence, the use of low power processors such as Intel Atom and ARM Cortex have recently gained more interest. In this article, we compare performance and energy efficiency of cutting-edge high-density HPC platform enclosures featuring either very high-performing processors such as Intel Core i7 or E7 yet having low power-efficiency, or the reverse i.e. energy efficient processors such as Intel Atom, AMD Fusion or ARM Cortex A9 yet with limited computing capacity. Our objective was to quantify in a very pragmatic way these general purpose CPUs using a set of reference benchmarks and applications run in an HPC environment, the trade-off that could exist between computing and power efficiency.

Wireless sensor network has many advantages. One of the primary benefits is their independence from the wiring costs and constraints, which makes it is suitable for monitoring the environmental conditions around the high-speed railway. However, the energy of the sensor node is limited and railways are often located in remote area. If batteries have to be replaced frequently, the initial cost savings will be lost. Therefore, power efficiency is a critical requirement for wireless sensor networks. In this paper, two algorithms have been investigated for application of wireless sensor network in Railway Disaster Prevention and Safety Monitoring System, which are Advanced Direction-aware Algorithm and Cluster Head Selection Algorithm based on the Dynamic Energy Threshold respectively. Theoretically, both algorithms can effectively extend the lifetime of the wireless sensor network.

Phased array antenna has many technical advantages: high power efficiency, shaped beam, fast tracking by electric scanning, high stealth performance. If the array elements distribute on the airframe surface, the shape of the array is the same as the airframe contour, then the array is a conformal phased array. Conformal phased array has many advantages compared to planar phased array: smaller volume, no effect to aerodynamic performance of aircrafts, wider scanning range. In a conformal array, antenna elements are not placed in one plane because of its conformal structure. So the array elements and array factors cannot be separated, and the polarization direction of each element is different from each other, which will cause severe cross-polarization component. A field vector synthesis method is used in this paper to analyze the pattern of conformal phased array antenna, which can avoid dealing with the array element and array factor. This method is suitable for conformal array of any shape. This method is verified by calculating the pattern of a conformal array of truncated cone shape.

Hybrid/Electric Vehicles are expected to be one of the solutions for energy and environmental problems. Up to Now, low power automotive electronics have operated under a battery voltage of 12 V and a large current of more than 10 A. Because of this high current, the power electronic circuits cause substantial losses of power through wire harnesses, a DC/DC converter, semiconductors, and so on. In this paper, we have proposed a novel concept of high voltage auxiliaries, which replaces the 12 V loads with the high voltage loads driven directly by the high voltage battery. It is assured that the power efficiency of the high voltage test system is as high as 94 %, which is at least 10 % higher than that of conventional 12 V blower motor systems.

Computer architecture in recent years shifted focus from performance to power efficiency (a combined metric or performance and energy consumption). For decades architects translated Moore’s law into performance, but we are now close to hitting two major “walls”: The first is the “power wall,” or our inability to significantly reduce power consumption (and more importantly power density). The power wall is likely to lead us to a “dark silicon” future where the majority of the transistors on a chip will have to be turned off because of power constraints. The second is the “memory wall.” Because, fundamentally, our current memory technology can be fast or vast, but not both at the same time, we have to rely on a complex memory hierarchy which, nevertheless, has significant limitations. In addition to power and performance, architects also worry about reliability. As we scale to very small feature sizes, devices become increasingly unreliable. A new trend that is emerging, however, is to embrace unreliability rather than fight it. This chapter discusses the challenges computer architects are facing today and the possible connections at the architectural level with novel devices that are in development.

Linearity and power efficiency of transmitter are the two major concerns in designing modern wireless communication system. Consequently various competitive and complementary technologies have been investigated. The design techniques of high efficiency power amplifier and advanced linearity transmitter architecture are generally introduced in this paper, and the implementation of several efficiency enhanced power amplifiers, such as Doherty power amplifier, inverse class E power amplifier with series tunable parallel resonant tank, multiband high efficiency power amplifier based on CRLH transmission lines and wideband (0.9–2.7 GHz) high efficiency power amplifier, are also presented. Furthermore, digital predistortion is used to increase the linearity of inverse class E power amplifier, and a high degree of spectral suppression for out-of-band is achieved. Moreover, the telemetry transmitter, which is suitable for 2 Mbps PCM signal, is developed based on high efficiency class E power amplifier. The results show the switching mode amplifiers have potential application in improving the power efficiency of telemetry transmitter.

Increasing air pollution in recent decades has raised many environmental concerns and affected the operation of electric power plants. On the other hand, energy storage systems with their fast-developing technologies are interesting options to be used with various goals in planning and operation of power systems. In this chapter, the power system operation with the Battery Energy Storage Systems (BESS) is analyzed and mathematically modeled in order to manage and control emission of power plants. Also, the life-time parameters of the BESS are considered in the problem modeling. The proposed model is optimized using a hybrid optimization approach which is based on combination of the (-iteration based economic load dispatch and genetic algorithm. The proposed approach is applied to a 69-bus system and the optimal parameters of the BESS are obtained. These parameters include the charge and discharge power and the stored energy of the BESS as well as its corresponding idle hours. The obtained results show that BESS can be used as an effective option for emission control of power plants.

OLED (Organic light-emitting) displays have been called the next generation of display devices for their unique properties: colorful images, large viewing angle, light weight and power efficiency. Complex manufacture processing makes the screen have some defects. Detecting the defects will help to improve the quality. In this paper we concentrate on detecting these defects and proposed a corner-points based method, where the corner-points are extracted from the skeleton image and used as the control points for the subtract operation. We proposed an improved Otsu method to determine the image segmentation threshold by recursive process. Based on the algorithm proposed, a system for OLED screen defect detection was developed. The test result shows that the developed system can detect most of the defects on the panel.

In the future it is very likely that asymmetric multi-core processors (AMP) will be used because of their proposed power efficiency and higher performance. In order to use the device intelligently and efficiently, it is essential to exploit the heterogeneity of AMPs. To fully exploit AMP systems, intelligent scheduling of tasks or intelligent resource management becomes one of the critical issues. In this paper, an AMP system is emulated, SPEC CPU2006 benchmark applications are executed as tasks, and heuristic methods for task scheduling are designed. Tasks are independent, non-preemptive, and have deadline (hard real-time) constraints. They arrive aperiodically and task migration is enabled. The performance metric is the total number of tasks completed by their deadline. The heuristic methods that are designed are compared with classic methods and the naive Linux scheduler. Experimental results show that our task scheduling method completed 2.8 times more tasks than the naive Linux scheduler for the proposed AMP environment.

For mobile communication systems power efficiency is a very important issue. Especially for mobile user equipments a careful management and efficient use of the limited energy ressources is mandatory. In today's user equipments quite an amount of energy is wasted. The reason for this is, that analog and digital frontend in communication systems are engineered for extracting the wanted signal from a spectral environment, which is defined in the corresponding communication standards with strict requirements. In a real receiving process those requirements can typically be considered as less critical. Sensing the environmental transmission conditions and adapting the receiver architecture to the actual needs allows to save energy during the receiving process. An efficient architecture being able to fulfill this task for a typical Long Term Evolution scenario has been disussed recently. For the implementation of this architecture, highly efficient filter approaches had to be investigated. This paper gives an overview on the basic properties of those approaches and compares it to well known filter types.

In this paper, author examines the use of on-off keying (OOK) and pulse-position modulation (PPM) and differential pulse-position modulation (DPPM) for visual light positioning systems, presents expressions for the error probability and synchronization failure probability and power spectral density of OOK, PPM and DPPM, gives structure design to realize PPM and DPPM based on existing OOK systems. Finally, it is shown that for a given bandwidth, the performance of 2M-DPPM is better than the performance of M-PPM, while the system structure of DPPM is simpler.

Due to high operation efficiency and control flexibility, the AC excited double-fed induction generator can not only realize Variable-speed constant-frequency (VSCF), a new typed operational mode for the doubly fed induction generator based wind power generation system is proposed based on the grid-connected power transmission. A control method aimed at increasing efficiency and maximizing energy capture using the stator flux-orientation control technology is introduced. the excitation controller was achieved using fuzzy-PID control. The results of simulation and experimental study testify the feasibility of the proposed strategy, meanwhile validate the optimal power efficiency tracking and optimal wind power capturing can be achieved.

Computer systems with discrete GPUs are expected to become the standard methodology for high-speed encryption processing, but they require large amounts of power consumption and are inapplicable to embedded devices. Therefore, we have specifically examined a new heterogeneous multicore processor with CPU---GPU integration architecture. We first implemented three 128-bit block ciphers (AES, Camellia, and SC2000) from several symmetric block ciphers in an e-government recommended ciphers list by CRYPTREC in Japan using OpenCL on AMD E-350 APU with CPU---GPU integration architecture and two traditional systems with discrete GPUs. Then we evaluated their respective power efficiencies. Result showed that performance per watt of AES-128 on the APU including 80 cores were 743.0 Mbps/W and 44.0 % increases compared with those on a system equipped with a discrete AMD Radeon HD 6770 including 800 cores. This paper is the first to describe a study to evaluate the per-watt performance of block ciphers on GPUs.

The radio frequency (RF) power amplifier (PA) is one of the most critical components in designing transmitters in wireless communication systems, and its efficiency dominates the overall efficiency of the transmitter. On one hand, the PA is most power consuming ; for example, in a cellular phone, the battery life is largely determined by the power efficiency of the PA. On the other hand, it is desirable to have the ability to transmit data at the highest possible rate for a given channel bandwidth, i.e., to have high spectral efficiency [1].

In order to increase electric cars power efficiency when control frequency conversion, and reduce the interference of high harmonics, we propose a design method of voltage space vector (SVPWM) frequency conversion control module. Based on TMS320LF2407 the PWM signal producing module design, IPM module as the core, we design the inverter circuit and Developed SVPWM real-time motion control program. This program use the manner of segmentation modulation, achieve frequency conversion control a range of 5 ~ 100Hz frequency. Variable frequency speed-governing experiment shows that, The control method can reduce the switching losses, meanwhile suppress the temperature rise.

Obstacle avoidance of Micro Aerial Vehicle (MAV) in urban environment is the most complex, difficult and essential part of the autonomous flight problems. The paper presents a simple ad-hoc strategy using a pair of miniature laser rangefinders (i.e. MLR100) and two PIDs cooperating with an obstacle avoidance controller. The strategy can be realized as an additional routine integrated with the autopilot’s firmware (i.e. MP2128HELI). The main advantage of the proposed strategy is simplicity of its implementation in small-sized MAVs and its power efficiency. All previous works, especially the vision-based ones require high performance microprocessors which is an important limitation when applying on real MAVs. On the other hand, the autonomous controller, which is based on optic flow sensors, is easy to implement on even tiny MAVs, but optic flow sensors require applicable level of contrast variation, so their performance is strongly sensitive to weather conditions. The proposed idea of the autonomous obstacle avoidance system in urban environment was simulated using MATLAB – SIMULINK software. In the real flight all computations and controls will be realized by the advanced autopilot, hence the rest of autonomous control and complex flight dynamics are not included in the simulation. The assumption allows to spot a more focused attention on the obstacle avoidance problem and a simpler model of the MAV can be used in the simulation. The results presenting the 2D trajectories confirm that the effectiveness and safety of the proposed strategy of obstacle avoidance is attainable during the real flight in streets’ canyons.

A low power 12-b 100-MSps pipeline analog-to-digital converter (ADC) is implemented in 0.18-μm CMOS process. The op-amp sharing with current selection between the front-end sample-and-hold (S/H) and the first stage multiplying digital-to-analog converter (MDAC) improves the power efficiency dramatically, and the application of range scaling technology decreases the power consumption further. A zero compensation method based on boot-strap technology is introduced in op-amp design to accomplish precise compensation as well as improve the linearity. The simulation result shows the ADC achieves an SFDR of 81 dB with a 50MHz input signal at 100-MSps. The DNL and INL are both within ±0.5LSB. The ADC consumes 46.5 mW from a 1.8V supply.

Chip-based electronics in 2010 consumed about 10% of the world’s total electric power of ∼2 TW. We have seen throughout the book that all segments, processing, memory and communication, are expected to increase their performance or bandwidth by three orders of magnitude in the decade until 2020. If this progress would be realized, the world semiconductor revenue could grow by 50–100%, and the ICT industry by 43–66% in this decade (Fig. 6.1). Progress sustained at these levels certainly depends on investments and qualified manpower, but energy has become another roadblock almost overnight. In this chapter, we touch upon the life-cycle energy of chips by assessing the energy of Si wafer manufacturing, needed to bring the chips to life, and the power efficiencies in their respective operations. An outstanding segment of power-hungry chip operations is that of operating data centers, often called server farms. Their total operating power was ∼36 GW in 2010, and we look at their evolution under the prospect of a 1,000× growth in performance by 2020. One feasible scenario is that we succeed in improving the power efficiency of Processing 1,000×, Memory 1,000×, Communication 100×, within a decade. In this case, the total required power for the world’s data centers would still increase 4× to 144 GW by 2020, equivalent to 40% of the total electrical power available in all of Europe. The power prospects for mobile/wireless as well as long-line cable/radio/satellite are equally serious. Any progression by less than the factors listed above will lead to economic growth smaller than the projections given above. This demands clearly that sustainable nanoelectronics must be minimum-energy (femtojoule) electronics.

Interconnects on-chip between transistors and between functions like processors and memories, between chips on carriers or in stacks, and the communication with the outside world have become a highly complex performance, reliability, cost, and energy challenge. Twelve layers of metal interconnects, produced by lithography, require, including the contact vias, 24 mask and process cycles on top of the process front-end. The resulting lines are associated with resistance, capacitance and inductance parasitics as well as with ageing due to high current densities. Large savings in wiring lengths are achieved with 3D integration: transistor stacking, chip stacking and TSV’s, a direction, which has exploded since 2005 because of many other benefits and, at the same time, with sensitive reliability and cost issues. On top of this or as an alternative, non-contact interconnects are possible with capacitive or inductive coupling. Inductive in particular has proven to be attractive because its transmission range is large enough for communication in chip stacks and yet not too large to cause interference.Optical transmitters based on integrated III-V compound-semiconductor lasers and THz power amplifiers compete with ascending low-cost, parallel-wire transmitters based on BiCMOS technologies. Parallel mm-wave and THz transceiver arrays enable mm-wave radar for traffic safety and THz computed-tomography. In spite of all these technology advances, the power efficiency of data communication will only improve 100× in a decade. New compression and architectural techniques are in high demand.

Energy cost in the data center is rising at a steep rate, and a significant portion of that cost comes from the storage system. Storage (disks and memory systems) accounts for more than 30% of the total power consumption. This number is expected to rise to 50% of the overall IT budget in the future. Enhancing the power efficiency of storage systems is of utmost importance, and, many techniques have been proposed and are being explored in both component and system levels. This chapter starts by providing a brief introduction on the basic power characteristics of storage components from a device-level perspective. Then several architectural and high-level power management techniques are covered.

In this paper, a new switching angle control methodology for inverters is developed to minish switching times to improve power efficiency. Based on Walsh transformation, it proposes a selective harmonic elimination-pulse width modulation (SHE-PWM) approach. The switching angles is obtained quickly, thus, for grid-connected photovoltaic system, realized is the online closed-loop control, obtaining unity power factor, improving system stability and effectively decreasing harmonic distortion. The simulation and experiment results validate the effectiveness of the control algorithm.

Power saving is one of the key issues in mobile ad-hoc networks (MANET), while previous researches in MAC layer are mostly focused on improving the channel utilization by adopting variable-range transmission power control. In this paper we focus on the power savings in the network layer, and propose a power adjusting algorithm (we term it PAA). In the presence of mobile host's mobility, PAA is designed to conserve energy by adjusting the transmission power to maintain the route's connectivity and restarting the route discovery periodically to find the new better route dynamically. After analyzing the operations of PAA, we find that the length of route discovery restarted period is a critical argument which will affect power saving, so we propose an optimizing model which finds the optimal value of this argument by analyzing the energy consumption of this algorithm. PAA can handle the mobility of MANET by adjusting the transmission power and in the meantime save energy by restarting route discovery periodically to balance the energy consumption on route discovery and packets delivering. It is suggested that PAA can be implemented in the dynamic source routing protocol (DSR). Simulation results are provided, which demonstrate DSR embedded with PAA saves nearly 40% energy compared to DSR without PAA in the presence of high mobility.

Wireless mobile, cabled xDSL, Fiber Optical Systems and Power Line Communications share a common problem: Bandwidth-Power efficiencies. While the efficiency required for the spectrum usage is different from wireless to wireline since the former has to respect some standardization bodies recommendations and the latter is mainly tied to channel quality aspects, the power efficiency is mainly linked to electrical power that comes from different sources like carbon, gas, oil, wind, solar, water. Unfortunately only few of these are renewable and require institutional investments for the medium-far future. In the meantime the only one way to be run appears to be the efficient. From this the necessity, in a Green-IT vision, to propose schemes, architectures, protocols and algorithms able to optimally manage bandwidth and power so to guarantee the expected performance at a reasonable cost. This is the direction currently followed by scientific community for already existing systems and in-developing new technologies.

This paper analyses two methods of organizing parallelism for the Smith-Waterman algorithm, and show how they perform relative to peak performance when the amount of parallelism varies. A novel systolic design is introduced, with a processing element optimized for computing the affine gap cost function. Our FPGA design is significantly more energy-efficient than GPU designs. For example, our design for the XC5VLX330T FPGA achieves around 16 GCUPS/W, while CPUs and GPUs have a power efficiency of lower than 0.5 GCUPS/W.