1. Evaluation of a low-power reconfigurable DSP architecture
- Author
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Marlene Wan, A. Abnous, Jan M. Rabaey, Katsunori Seno, and Yuji Ichikawa
- Subjects
Signal processing ,business.industry ,Computer science ,Embedded system ,Control reconfiguration ,Digital signal ,Architecture ,business ,Field-programmable gate array ,Dsp architecture ,Digital signal processing ,Power (physics) - Abstract
Programmability is an important capability that provides flexible computing devices, but it incurs significant performance and power penalties. We have proposed an architecture that relies on dynamic reconfiguration of hardware resources to implement low-power and programmable processors for DSP applications. In this paper, we evaluate this architectural approach and compare it to other programmable architectures.
- Published
- 1998
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