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The Compute Unified Device Architecture (CUDA) programming environment from NVIDIA is a milestone towards making programming many-core GPUs more flexible to programmers. However, there are still many challenges for programmers when using CUDA. One is how to deal with GPU device memory, and data transfer between host memory and GPU device memory explicitly. In this study, source-to-source compiling and runtime library technologies are used to implement an experimental programming system based on CUDA, called memCUDA, which can automatically map GPU device memory to host memory. With some pragma directive language, programmer can directly use host memory in CUDA kernel functions, during which the tedious and error-prone data transfer and device memory management are shielded from programmer. The performance is also improved with some near-optimal technologies. Experiment results show that memCUDA programs can get similar effect with well-optimized CUDA programs with more compact source code.

It is a difficult issue to support interactive image processing software in grid environment, which requires special mapping methods over grid architecture Interactive service packaging, mapping of interactive interface mechanism are reviewed in heterogeneous grid architecture Grid Service Automated Packaging and Generating System (GS-APGS) for image processing software is designed to provide grid service packaging and generating tools to create friendly human-machine interfaces It includes interactive operation-message mapping in packaging, service-message mapping feedback control in grid service generation, and preservation and restoration of continuous interactive state in overall mapping Experiments show that GA-APGS can reduce more than 50% time on service packaging and deployment than terminal command-line mode.

Medical diagnosis and intervention increasingly rely upon medical image processing tools that are bound with high-cost hardware, designed for special diseases, and incapable of being shared by common medical terminals. In this paper, we present our Ubiquitous Context-based Image Processing Engine (UCIPE) for MedImGrid (Medical Image Grid). It encapsulates image processing algorithms as WS (Web Services), and creates virtual algorithm barn to store their metadata. The user contexts are captured by UCIPE clients and used as clues to search the optimal WS from the algorithm barn. UCIPE supports all-weather accesses (anytime, anywhere, with any means) of numerous multiple terminals to guarantee the algorithm resources be accessed transparently. The UCIPE prototype for MedImGrid is based on CERNET2. The performances of UCIPE-based 3D reconstruction verify the feasibility of UCIPE and prove the improvement of IPv6 network to medical gird applications.

MIGP (Medical Image Grid Platform) realizes information retrieval and integration in extensive distributed medical information systems, which adapts to the essential requirement for the development of healthcare information infrastructure. But the existing MIGPs, which are constructed mostly based on database middleware, are very difficult to guarantee local hospital data security and remote accessing legality. In this paper, a MIGP based on the WSRF-compliant HL7 (Health Level 7) grid middleware is proposed, which aims to combine the existing HL7 protocol and grid technology to realize medical data and image retrieval through the communications and interoperations with different hospital information systems. We also design the architecture and bring forward a metadata-based scheduling mechanism for our grid platforms. At last, experimental MIGPs are constructed to evaluate the performance of our method.

Computational grids have become a vital emerging platform for high-performance computing. However, some obstacles for the prevalence of grid and the grid application development are still far from mature, which is largely due to the immature grid-enabled computing environment. Image-Processing Grid Environment (IPGE) is a project that aims at providing high performance image-processing platform in a grid computing environment. IPGE is a combination of components and workflow techniques on which complex applications can be modelled as grid workflows with local or grid-enabled remote service components. In this paper, we discuss the infrastructure to provide the integration platform with both techniques, which provides flexible and useful mechanism and scheduling strategy to achieve series image processing operations. Components and workflow techniques provide benefits of flexibility, reusability and scalability and to construct cooperative image-processing applications easily.

Computational grids have become attractive and promising platforms for solving large-scale high-performance applications of multi-institutional interest. However, the management of resources and computational tasks is a critical and complex undertaking as they are geographically distributed, heterogeneous in nature, owned by different individuals or organizations with their own policies, different access, and dynamically varying loads and availability. In this paper, we propose an integrated management and scheduling scheme for computational grid. It solves some pivotal and important questions such as resources heterogeneous and information dynamic. It affords transparent support for high-level software and grid applications, enhancing the performance, expansibility and usability of computers, and providing incorporate environment and information service. This scheme has universality for computational grid and makes every grid resource work efficiently.

Part 5: Session 5: Miscellaneous; International audience; Memory vulnerabilities have severely affect system security and availability. Although there are a number of solutions proposed to defense against memory vulnerabilities, most of existing solutions protect the entire life cycle of the application or survive attacks after detecting attacks. This paper presents OPSafe, a system that make applications safely survive memory vulnerabilities for a period of time from the starting or in runtime with users’ demand. OPSafe can provide a hot-portable Green Zone of any size with users’ demand, where all the subsequent allocated memory objects including stack objects and heap objects are reallocated and safely managed in a protected memory area. When users open the green zone, OPSafe uses a comprehensive memory management in the protected memory area to adaptively allocate buffers with multiple times of their defined sizes and randomly place them. Combined with objects free masking techniques, OPSafe can avoid overrunning each other and dangling pointer errors as well as double free or invalid free errors. Once closing the green zone, OPSafe clears away all objects in the protected area and then frees the protected area. We have developed a Linux prototype and evaluated it using four applications which contains a wide range of vulnerabilities. The experimental results show that OPSafe can conveniently create and destruct a hot-portable green zone where the vulnerable application can survive crashes and eliminate erroneous execution.

Part 4: Session 4: Multi-core Computing and GPU; International audience; Transactional memory is an appealing technology which frees programmer from lock-based programming. However, most of current hardware transactional memory systems are proposed for multi-core processors, and may face some challenges with the increasing of processor cores in many-core systems, such as inefficient utilization of transactional buffers, unsolved problem of transactional buffer overflow, etc. This paper proposes PM_TM, a hardware transactional memory for many-core processors. The system turns transactional buffers that are traditionally private to processor cores into shared by moving them from L1-level to L2-level, and uses partition mechanism to provide logically independent and dynamically expandable transactional buffers to transactional threads. As the result, the solution can utilize transactional buffers more efficient and moderate the problem of transactional buffer overflow. The system is simulated and evaluated using gems and simics simulator with STAMP benchmarks. Evaluation results show that the system achieves better performance and scalability than traditional solutions in many-core processors.

Part 1: Session 1: Parallel Programming and Algorithms; International audience; Concurrent programs are difficult to debug due to the inherent concurrence and indeterminism. One of the problems is race conditions. Previous work on dynamic race detection includes fast but imprecise methods that report false alarms, and slow but precise ones that never report false alarms. Some researchers have combined these two methods. However, the overhead is still massive. This paper exploits the insight that full record on detector is unnecessary in most cases. Even prior sampling method has something to do to reduce overhead with precision guaranteed. That is, we can use a frequency-sensitive sampling approach. With our model on sampling dispatch, we can drop most unnecessary detection overhead. Experiment results on DaCapo benchmarks show that our heuristic sampling race detector is performance-faster and overhead-lower than traditional race detectors with no loss in precision, while never reporting false alarms.

International audience; It is well known that image compositing is the bottleneck in Sort-Last rendering. Many methods have been developed to reduce the compositing time. In this paper, we present a series of pipeline methods for image compositing. Our new pipeline methods based on Direct Send and Binary Swap. However, unlike these methods, our methods overlap the rendering time of different frames to achieve high fps(frames per second) in final display. We analyze the theoretical performance of our methods and take intensive experiments using real data. The results show that our new methods are able to achieve interactive frame rates and scale well with both the size of nodes and screen resolution.

International audience; Cluster-based storage systems connected with TCP/IP networks are expected to achieve a high throughput by striping files across multiple storage servers. However, for the storage system interconnected with the TCP/IP network, several critical issues, like Incast effect and data access interference, invalidate the assumption that higher access parallelism always results in increased I/O throughput. To address this issue, we propose a new file striping strategy, named as storage server grouping (SSG), which changes file striping pattern across the storage servers based on the analysis of file popularity and impact of the number of storage servers on the clients' perceived performance (I/O speedup) to reduce the interference of data accesses to popular files and avoid dramatic reduction of system throughput caused by the Incast effect. Our experimental evaluation shows that SSG can improve I/O throughput by 22.1% on average.