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In this paper, we propose a low complexity algorithm to jointly demosaic and denoise Bayer format image, which combines the Hamilton and Adams (HA) method for interpolation and Epsilon filter for noise removal. Instead of using a 5x5 filtering window, one 7x1 horizontal Epsilon filter and one 1x3 vertical Epsilon filter are adopted in our method, which reduces hardware cost significantly while keeps high performance. Simulation results show that our proposed algorithm improves the mean PSNR performance of image by 1 dB compared to the algorithms treating these two processes independently. Furthermore, only 4 line buffers are consumed, and simple logic operators including adders and shifters are used for computation. For real-time implementation, a 5 stage pipelined VLSI architecture with 24 kb SRAM for line buffer is presented. The prototype of the joint processor is verified with Xilinx FPGA device and consumes about 36.6K gates for computational logic after synthesis with TSMC 90nm technology. The joint processor achieves a throughput of 6 Gbps at 250 MHz.

This paper presents a reduced-complexity soft-input soft-output parallel stack algorithm (SISO-PSA) for multiple-input multiple-output (MIMO) wireless communication systems employing Turbo iterative processing at the receiver. The proposed algorithm incorporates hybrid enumeration and a modified tree pruning criterion to support soft-inputs, which results in significant computational complexity saving. Moreover, a leaf enumeration scheme is proposed to reduce the number of expanded leaf nodes. In addition, the parallelism at algorithm level provides high throughput while reduces area compared to hardware level parallelism, which is very suitable for VLSI implementation. The simulation results show that the proposed algorithm can achieve better performance than SISO K-Best algorithm (K=50) and SISO-FSD with 60% memory saving and significantly reduced computational complexity in terms of the number of visited nodes in a 4(4 64QAM MIMO system.

Ever growing power density has made thermal effects one of the most crucial issues for modern VLSI designs, e.g., reports have shown that more than 50% of IC failures are related to thermal issues. However, thermal issues for Coarse Grain Reconfigurable Architectures (CGRA) have been few addressed. In this paper, a thermal-aware task mapping algorithm called Max-Min algorithm is developed for the REmus reconfigurable architecture, which uses compact thermal model based on equivalent thermal circuit to iteratively optimize the power dissipation on the modern CGRAs. Experiments based on Hotspot simulation show that the algorithm can reduce the maximum temperature by 3~9℃ and narrow the temperature distribution range by 7~15℃. Compared to previous intuitive random algorithm, the Max-Min algorithm can significantly reduce the number of optimization iterations while reserving the same result.