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All-inkjet-printing of transistors has received much attention for low cost and flexible integrated circuits. However, most flexible field-effect transistors (FETs) based on the emerging two-dimensional materials suffer from the high cost of substrate and electrode materials. The requirements for high-temperature synthesis and precise control in processing add another layer of complexity. To overcome these issues, low-cost flexible paper-based MoS2 FETs were fabricated by inkjet printing of MoS2 channel materials on paper. Additionally, we proposed and achieved the mask-less and low-temperature formation of source and drain electrodes on paper using in-situ selective-area copper reduction. A low sub-threshold swing of 80 mV/dec, high on/off ratio of 105, and very high turn-on current (Ion) of 200 μA of the paper-based flexible MoS2 FETs were demonstrated using the proposed low-cost and facile all-inkjet-printing technique. The all-inkjet-printing technique assisted by in-situ copper reduction opens new opportunities for low-cost and batch fabrication of paper-based electronic devices in ambient conditions. [ABSTRACT FROM AUTHOR]

This paper proposes a visual management scheme of medical things with a color-change radio frequency identification (RFID) tag. The color-change RFID tag employs a specific RFID tag integrated circuit (IC) and a laminated pH-indicating paper. The IC has energy harvesting and switched ground functions, which enable it to generate electricity to the laminated pH-indicating paper. This phenomenon causes electrolysis of NaCl solution absorbed in the laminated pH-indicating paper. Electrolysis generates alkaline matter to change the color of the pH-indicating paper. This paper gives a new and sensitive structure of the laminated pH-indicating paper. The proposed advanced color-change RFID tag with new laminated pH-indicating paper succeeds in changing its color noticeably at a 1 m distance using an RFID reader radiating 1 W radio waves. The color change was observed 3–5 s after starting radio wave irradiation. The results of this experiment also confirm that the changed color can be held for over 24 h. Furthermore, two demonstrations of the visual management system of medical things (patient clothes and sanitizers) are presented. [ABSTRACT FROM AUTHOR]

This special issue contains papers obtained through open call-for-papers as well as from the selected extended versions of the papers presented in the 4th International Conference "2021 Devices for Integrated Circuit (DevIC)", held at Kalyani Government Engineering College from May 19-20, 2021. This special issue publishes a collection of papers that were submitted to the Journal of Materials Science: Materials in Electronics on the theme of experimental electronic and optical materials for nano-dimensional device applications. [Extracted from the article]

Origami, an ancient form of papercraft, provides a way to develop functional structures for engineering applications. In this paper, we report an approach to design and manufacture a stretchable circuit board (SCB) with origami structures. The benefits of developable, flat-foldable, and rigid-foldable origami-based structures as SCBs are discussed, and a representative structure, Miura fold (or Miura-ori), is chosen to be investigated. Under the constraints induced by the mounted components' dimensions, the Miura-ori structures for specific applications can be defined. We propose three methods for better fabrication, including direct folding, stiffness modification, and kirigami enhancement, to improve a planar sheet's foldability. A wearable ECG (electrocardiogram) system based on MO-SCB (Miura-ori enabled SCB) technology is built, and the stretchable portion is made of commercial FPCBs (flexible printed circuit board), providing desired stretchability and reliability. The proposed technology routine is compatible with industrial production and may pave the application of stretchable electronics. [ABSTRACT FROM AUTHOR]

This paper introduces a novel, cost-effective solution designed to achieve large absorption bandwidth within the THz spectrum employing a miniaturized, single-layer metamaterial structure. The designed structure features a single circular ring composed of an ohmic resistive sheet with notably higher sheet resistance than traditional metallic resonators. This distinctive design is implemented on a lossy dielectric polyimide substrate with a backing of metallic gold. Our developed absorbing structure demonstrates the capability to achieve a substantial absorption bandwidth ranging from 3.78 to 4.25 THz, maintaining a consistent absorption rate of over 90%. Moreover, we conducted an analysis to assess its absorption performance under various sheet resistance values within the top layer. Additionally, we characterized its angular stability and polarization insensitivity through oblique incident and polarization angle analysis. Finally, an RLC circuital and interference theory approach is adopted to justify its simulated results. The proposed absorber shows potential for a broad spectrum of applications, encompassing communication, imaging, and diverse integrated circuits operating within the THz band. [ABSTRACT FROM AUTHOR]

This paper explores the influence of temperature on the scattering mechanism of multilayer graphene nanoribbon (MLGNR). A thermally aware electrical ESC model along with mathematical computations is presented for evaluating the parasitic and reports the performance analysis dependent on temperature of the MLGNR at global interconnect length for 16 nm, 22 nm, and 32 nm nodes of technology in terms of power dissipation, delay, and power delay product (PDP). It was examined that with rising temperature, there is a strident decrease in the mean free path of GNR interconnect, which further influence its own resistance at variable global lengths (500‒2000 μm) for all three technology nodes. The simulation program with integrated circuit (SPICE) emphasis simulation tool is used to estimate and compare the performance of MLGNR in terms of power dissipation, signal delay and PDP for three different nodes of technology. It is revealed from the outcomes that the propagation delay and PDP increase at long interconnects (2000 μm) over a temperature range of 200 to 500 K for deep submicron technology nodes (16, 22, and 32 nm). Further, based on ITRS 2013, the analytical and simulated results are obtained at global interconnect length (2000 μm) for 16 nm technology node in the 200–500 K temperature range of MLGNR. The simulation and analytical results show that the outcomes of the two models are very similar. The models' trends show an increase in delay with increasing temperature levels (200‒500 K) 16 nm technology node. [ABSTRACT FROM AUTHOR]

The dielectric loss of Cu with high thermal conductivity is large at high frequency, which cannot meet the performance requirements in high-integrated circuits. There is an urgent need for materials to reduce its dielectric loss. In this paper, the thermal conductivity and dielectric properties of the AlN coating-Cu substrate system were controlled by changing the N2 pressure. The results showed that the crystallinity of hcp-AlN in AlN coating increased significantly when the proportion of N2 pressure was increased. With the increase of the N2 pressure, the particle size on the surface and the roughness of the coating improved. The AlN coating prepared at high N2 pressure had high dielectric constant and low dielectric loss at high frequency compared to those of the coatings prepared at low N2 pressure. At the same time, the AlN coating prepared under high N2 pressure on the Cu substrate did not decrease the thermal conductivity of Cu substrate. The AlN-Cu system prepared in this paper had high thermal conductivity and good dielectric properties, providing theoretical guidance for integrated circuit packaging and capacitor applications. [ABSTRACT FROM AUTHOR]

In this paper the design of power management integrated circuits for the energy harvesting of ultrasound waves in implanted biomedical devices is addressed. In particular, the paper focuses on the main building block of the power conversion stage which is represented by the AC/DC converter. After an in-depth analytical description of cross-coupled passive and active rectifiers, a detailed design procedure for the common-gate comparator is introduced. Then a comparison between the different discussed topologies is carried through simulation results using a 28-nm standard CMOS technology. The results provide useful design guidelines in choosing the best topology according to the design specifications. [ABSTRACT FROM AUTHOR]

The piezoelectric coupling principle is widely used (along with capacitive coupling and piezoresistive coupling) for MEMS accelerometers. Piezoelectric MEMS accelerometers are used primarily for vibration monitoring. Polymer piezoelectric MEMS accelerometers offer the merits of heavy-metal-free structure material and simple microfabrication flow. More importantly, polymeric piezoelectric MEMS accelerometers may be the basis of novel applications, such as fully organic inertial sensing microsystems using polymer sensors and organic integrated circuits. This paper presents a novel polymer piezoelectric MEMS accelerometer design using PVDF films. A simple and rapid microfabrication flow based on laser micromachining of thin films and 3D stereolithography was developed to fabricate three samples of this design. During proof-of-concept experiments, the design achieved a sensitivity of 21.82 pC/g (equivalent open-circuit voltage sensitivity: 126.32 mV/g), a 5% flat band of 58.5 Hz, and a noise density of 6.02 µg/√Hz. Thus, this design rivals state-of-the-art PZT-based counterparts in charge sensitivity and noise density, and it surpasses the performance capabilities of several commercial MEMS accelerometers. Moreover, this design has a 10-times smaller device area and a 4-times larger flat band than previous state-of-the-art organic piezoelectric MEMS accelerometers. These experimentally validated performance metrics demonstrate the promising application potential of the polymeric piezoelectric MEMS accelerometer design presented in this article. [ABSTRACT FROM AUTHOR]

Medical implants and portable wireless sensors are the most serious of biomedical applications due to the dependence on limited battery lifetime. Consequently, energy efficiency integrated circuits designs must be put to higher attention. A particular distinguishing contribution of this paper is its focus on the power consumption that affects battery life and the heat dissipated for biomedical applications. This paper demonstrates a power-efficient implementation of analog-to-digital converter (ADC) based on voltage-controlled oscillator (VCO) to convert the collected analog vital signs into digital data for digital signal processing. The current-starved scheme is employed to implement the VCO efficiently with five-stage which leads to high savings in power and area. D-flip flop (D-FF) scheme is proposed to simplify the hardware architecture of the proposed reset counter. The proposed architecture is implemented with 130 nm CMOS technology and it can perform conversion of analog input signal to digital output using a straightforward hardware structure. The proposed VCO-based ADC achieves improvement in energy saving. Simulation results confirm that this work attains a power dissipation of 0.257 mW and active area of 0.007 mm2, and a very good Walden FOMW of 125 dB. The proposed methodology can implement any number of bits of the ADC by using the appropriate voltage-controlled oscillator with the convenient reset counter. [ABSTRACT FROM AUTHOR]

Semiconductor wafer manufacturing relies on the precise control of various performance metrics to ensure the quality and reliability of integrated circuits. In particular, GaN has properties that are advantageous for high voltage and high frequency power devices; however, defects in the substrate growth and manufacturing are preventing vertical devices from performing optimally. This paper explores the application of machine learning techniques utilizing data obtained from optical profilometry as input variables to predict the probability of a wafer meeting performance metrics, specifically the breakdown voltage (Vbk). By incorporating machine learning techniques, it is possible to reliably predict performance metrics that cause devices to fail at low voltage. For diodes that fail at a higher (but still below theoretical) breakdown voltage, alternative inspection methods or a combination of several experimental techniques may be necessary. [ABSTRACT FROM AUTHOR]

Recently, interest in programmable photonics integrated circuits has grown as a potential hardware framework for deep neural networks, quantum computing, and field programmable arrays (FPGAs). However, these circuits are constrained by the limited tuning speed and large power consumption of the phase shifters used. In this paper, we introduce the memresonator, a metal-oxide memristor heterogeneously integrated with a microring resonator, as a non-volatile silicon photonic phase shifter. These devices are capable of retention times of 12 hours, switching voltages lower than 5 V, and an endurance of 1000 switching cycles. Also, these memresonators have been switched using 300 ps long voltage pulses with a record low switching energy of 0.15 pJ. Furthermore, these memresonators are fabricated on a heterogeneous III-V-on-Si platform capable of integrating a rich family of active and passive optoelectronic devices directly on-chip to enable in-memory photonic computing and further advance the scalability of integrated photonic processors. Photonic integrated circuits have grown as potential hardware for neural networks and quantum computing, yet the tuning speed and large power consumption limited the application. Here, authors introduce the memresonator, a memristor heterogeneously integrated with a microring resonator, as a non-volatile silicon photonic phase shifter to address these limitations. [ABSTRACT FROM AUTHOR]

Encryption chips are specialized integrated circuits that incorporate encryption algorithms for data encryption and decryption, ensuring data confidentiality and security. In China, the domestic SM4 algorithm is commonly utilized, as opposed to the international AES encryption algorithm. These widely implemented encryption standards have been proven to be difficult to crack through crypt analysis methods Currently, power consumption side-channel attacks are the most prevalent method. They involve capturing power consumption data during the encryption process and subsequently recovering the encryption key from this data. The two leading methods are Differential Power Analysis (DPA) and machine learning techniques. DPA does not necessitate prior knowledge but relies heavily on the number of power consumption curves. With only 50 power consumption data points, the accuracy is a mere 80%. Machine learning methods require prior knowledge, achieving an accuracy rate above 95% with only 30 power traces, albeit with training times typically exceeding 15 min. In this paper, a distributed energy analysis attack approach was presented based on Correlation Power Analysis (CPA). The power consumption data was divided into 16 subsets, with each subset corresponding to 8 bytes of the key. By training each subset separately, the 8-byte key's corresponding power consumption data is reduced to only 100 dimensions, resulting in a 76% decrease in cracking time and a 3% improvement in cracking accuracy rate.This article also trains a more complex 256 classification model to directly crack the final key, achieving a success rate of 28% in cracking 128-bit passwords with only 1 power trace [ABSTRACT FROM AUTHOR]

B Abstract: b Integrated circuits (ICs) with a single chip (die) are typically tested with a test flow consisting of two test instances: (1) wafer sort for the bare chip and (2) package test for the packaged IC. For ICs with stacked chips - 3D Stacked ICs - there are many possible test instances, even more test flows, and no commonly used test flow. We implemented the TFSA, three straightforward test flow schemes and an exhaustive search, and experimentally compared the test flow schemes on three different test architecture design approaches. [Extracted from the article]

This paper proposes an inductor-less D-latch. In the proposed D-latch, negative feedback is used that makes input impedance appears to be inductive for the high-frequency input signal. The bandwidth is increased by around 23% due to this effect. Two applications are shown in this paper to verify the proposed latch operation: a pseudo-random binary sequence (PRBS) generator and a serializer. The speed of the PRBS generator and serializer has improved by 15.8% and 23% using the proposed latch, respectively. The post-layout simulation results in 90 nm CMOS technology with a power supply of 1 V prove the concept. To study functional correctness and scalability of the proposed architecture to lower technology nodes, 22 nm PTM model is used and verified the correct operation of the proposed architecture. [ABSTRACT FROM AUTHOR]

In this paper, a programmable low-power analog front-end (AFE) integrated circuit (IC) for biomedical signal monitoring systems is presented. The whole system includes four parts, instrumentation amplifiers (IA), programmable gain amplifiers (PGA), programmable bandwidth filters (PBF) and successive approximation register analog-to-digital convertors (SAR ADC). The proposed IA employs a pseudo-differential structure to enhance the input impedance of the system. A novel hybrid bandwidth extension technology is introduced in the proposed PGA to correct the low-frequency distortion and improve the low-frequency bandwidth. In the design of PBF, the current steering technology is applied to achieve an area-efficient and energy-efficient architecture. Furthermore, a novel efficient switching scheme and a self-calibration dynamic element matching method are presented in the design of SAR ADC to reduce the power consumption and eliminate the effect of capacitor mismatch. In 0.18 μm CMOS technology, this AFE IC consumes 46.8 μW and occupies 0.36 mm2. It achieves a variable gain from 40.4 to 55.1 dB under different modes designed for different biomedical signals. The spurious-free dynamic range and signal-to-noise plus distortion ratio of the proposed SAR ADC are 71.3 and 53.3 dB, respectively, along with a figure of merit of 0.18 pJ/conv. [ABSTRACT FROM AUTHOR]

The article discusses research by Jan Schroers and colleagues at Yale University exploring a class of amorphous metals called bulk metallic glasses (BMG). Topics include the difficulties in finding a low-cost yet durable means of molding tiny components such as those used in computer chips, how Schroers and colleagues were able to mold BMGs at nanoscale dimensions, and its potential application in the semiconductor industry.

Since 2007, methods that utilize side-channel data to detect hardware Trojan (HT) problems have been widely studied. Machine learning methods are widely used for hardware Trojan detection, but with the development of integrated circuits (ICs), better results are usually obtained using deep learning methods. In this paper, we propose an architecture inspired by Residual-Block and Dense-Block and combine it with SE Attention Mechanism, which we named the Res-Dense-SE-Net network. By combining residual connectivity, dense connectivity, and attention mechanism, the Res-Dense-SE-Net network can enjoy the advantages of these three network architectures at the same time, which can improve the expressiveness and performance of the model. The Res-Dense-SE-Net network can capture the key features in the image better, and it can solve the problems of gradient vanishing and feature transfer efficiently, which can in turn improve the classification accuracy and the generalization ability of the model. Based on the publicly available AES series of hardware Trojans from TrustHub and the publicly available hardware Trojan-side channel data by Faezi et al., we evaluate the effectiveness of the method proposed in this paper. The experimental results show that when a single Trojan exists, the method proposed in this paper has a high accuracy rate; and when multiple types of hardware Trojans exist at the same time and need to be categorized, the categories of hardware Trojans can also be effectively identified, and the categorization accuracy is high compared with the existing deep learning methods. [ABSTRACT FROM AUTHOR]

The author reflects on model based high level programming of embedded systems. He states that embedded systems are mostly used in automotive and avionics industries. He further states that most successful representatives of this trend of putting logic and mathematics behind design automation in embedded systems are synchronous languages. He argues that model-based programming is making its way in other fields of software engineering too

The Cu–Fe–P alloy is the mainstream material of IC lead frame at present, which plays a key role in electrical signal transmission and mechanical fixation between bearing chip and external circuit board. With the development of integrated circuits toward high integration and extreme miniaturization, copper alloy strips for lead frames are required to have excellent electrical and mechanical properties, as well as excellent softening resistance under short-term high temperature service conditions. In this paper, the effects of annealing temperature (300, 400, 500 °C) on texture orientation and strength, and precipitates characteristics (morphology, size, interfacial relationship, etc.) of as-cold rolled Cu–2.18Fe–0.03P alloy were studied by means of EBSD and TEM. It is found that annealing at low temperature does not change the texture type, but it affects the texture strength compared with the as-cold rolled alloy. Cubic texture {001} < 100 > and R-type texture {111} < 112 > appear in the annealed alloy. The texture strength increases with the increase in annealing temperature, and the preferred orientation is more obvious. In addition, we found that there are two kinds of precipitated phases in the copper matrix, namely spherical α-Fe phase and irregular Fe3P phase. We further find out the coexistence state of the two precipitates and their evolution with annealing temperature. With the increase in annealing temperature from 300 to 500 °C, the size of the main strengthening phase α-Fe increases and the orientation relationship between α-Fe phase and the matrix changes from coherent to semi-coherent. On this basis, we found that the decrease in texture strength, the change of coherence relationship of α-Fe phase, and the decrease in dislocation barrier are the main factors leading to the softening of Cu–2.18Fe–0.03P alloy at high temperature. The research results of this paper are meaningful in guiding the development of high-end copper alloy strip in the field of electronic information. [ABSTRACT FROM AUTHOR]

This paper introduces a novel, cost-effective solution designed to achieve large absorption bandwidth within the THz spectrum employing a miniaturized, single-layer metamaterial structure. The designed structure features a single circular ring composed of an ohmic resistive sheet with notably higher sheet resistance than traditional metallic resonators. This distinctive design is implemented on a lossy dielectric polyimide substrate with a backing of metallic gold. Our developed absorbing structure demonstrates the capability to achieve a substantial absorption bandwidth ranging from 3.78 to 4.25 THz, maintaining a consistent absorption rate of over 90%. Moreover, we conducted an analysis to assess its absorption performance under various sheet resistance values within the top layer. Additionally, we characterized its angular stability and polarization insensitivity through oblique incident and polarization angle analysis. Finally, an RLC circuital and interference theory approach is adopted to justify its simulated results. The proposed absorber shows potential for a broad spectrum of applications, encompassing communication, imaging, and diverse integrated circuits operating within the THz band. [ABSTRACT FROM AUTHOR]

Explores the progress and emerging trends in the kinetic aspects of analytical chemistry. Kinetics techniques for analytical chemistry; Millisecond kinetics on microchips; Characteristics of an ideal biosensor; Outlook for kinetic approaches.

This paper presents a compact and efficient integrated interface circuit for piezoelectric energy harvesting. While state-of-the-art interface circuits require either an external inductor or a significant number of additional capacitors to achieve high voltage flip and thus improve power efficiency, the proposed Full Active Rectifier on Flipping Capacitor (FAR-FC) is based on a reduced set of flipping capacitors and an active rectifier to efficiently flip the voltage across the piezoelectric transducer. In addition, this optimized SSHC circuit reaches better power efficiency when the piezoelectric transducer operates under low mechanical excitation, i.e. when the open-circuit voltage of the piezoelectric transducer is V o c = 1 V , while usually V o c ≥ 2 V in literature. Furthermore, the FAR-FC supports piezoelectric transducers with higher inherent capacitance values compared to those usually reported in literature, which makes the circuit potentially suitable for a larger variety of applications. The interface circuit was designed and fabricated in a 0.35 μm CMOS process. Measurement results show that the voltage flip efficiency goes up to 90 % . It also reveals that the proposed FAR-FC circuit achieves power performance up to 5.64 × higher than a conventional full-bridge rectifier. [ABSTRACT FROM AUTHOR]

The transformer is an important component of electrical engineering for many applications including those for integrated circuits. For integrated circuit applications, the use of a synthetic transformer has been recognised to be a viable option for a number of applications. This paper presents two new designs of electronically-controllable CMOS active transformers. The first preposition is based upon a capacitive T-network embedded between two active CMOS gyrators each of which has been obtained by a parallel back-to-back connection of one non-inverting and other inverting electronically-controllable CMOS transconductor. This circuit requires thirty-two MOSFETs, all operating in saturation region. The second design simulates an inductive T-network using two CMOS electronically-controllable floating inductors and one electronically-controllable CMOS grounded inductor thereby employing eighty MOSFETs. The first design offers the advantage of realising a step up as well as step down transformer by appropriate selections of the transconductances of two transconductors. The second design although uses a larger number of MOSFETs than the former but has the advantage of using three grounded capacitors which is a desirable from the view point of IC implementation. It may also be mentioned that using more MOSFETs does not increase layout area significantly since the capacitors require more layout area than all the MOSFETs put together. The workability of both the designs, along with their various performance characteristics and non-ideal analysis, has been well corroborated by computer simulations using SPICE software using 0.18 µm CMOS technology parameters. The application of the proposed circuits in the design of double tunned band pass filter has also been shown and its workability too has been validated by computer simulations using SPICE software. [ABSTRACT FROM AUTHOR]

The growing complexity of integrated circuits (ICs) brings expensive manufacturing test cost. Adaptive testing becomes an important way to save test cost by predicting die quality to reduce the actual test content. However, reducing test items often results in unacceptable levels of test quality degradation. An adaptive testing method is proposed in the paper to reduce test cost while guaranteeing test quality. Two quality predictors are trained with a subset of test items and spatial information for subsequent decisions. The dies are clustered according to the prediction results, and the clustering results are graded. The distribution of the different grade classes determines the die quality of each grade. Experimental results using fabricated wafers and the associated test data show that the proposed method reduces more than 42% of test items, and can achieve better test quality, reducing test escapes and yield losses by more than 90% in the Circuit Probing test (CP). [ABSTRACT FROM AUTHOR]

This paper continues the research on the circuit synthesis problem for a multiplexer function of logic algebra, which is a component of many integrated circuits and is also used in theoretical study. The exact value of the depth of a multiplexer with select lines in the standard basis is found under the assumption that the conjunction and disjunction gates are of depth 1 and the negation gate is of depth 0; the depth equals if . Thus, it follows from previous results that the exact depth value equals for all positive integers such that either or . Moreover, for , this value equals 2, and for , it equals either or . Similar results are also obtained for a basis consisting of all elementary conjunctions and elementary disjunctions of two variables. [ABSTRACT FROM AUTHOR]

Although analog-to-digital converters (ADCs) are critical components in mixed-signal integrated circuits (IC), their performance has not been improved significantly over the last decade. To achieve a radical improvement (compact, low power and reliable ADCs), spintronics can be considered as a proper candidate due to its compatibility with CMOS and wide applications in storage, neuromorphic computing, and so on. In this paper, a proof-of-concept of a 3-bit spin-CMOS Flash ADC using in-plane-anisotropy magnetic tunnel junctions (i-MTJs) with spin–orbit torque (SOT) switching mechanism is designed, fabricated and characterized. In this ADC, each MTJ plays the role of a comparator whose threshold is set by the engineering of the heavy metal (HM) width. Such an approach can reduce the ADC footprint. Monte-Carlo simulations based on the experimental measurements show the process variations/mismatch limits the accuracy of the proposed ADC to 2 bits. Moreover, the maximum differential nonlinearity (DNL) and integral nonlinearity (INL) are 0.739 LSB (least significant bit) and 0.7319 LSB, respectively. [ABSTRACT FROM AUTHOR]

In this paper, we propose the design of a track and hold (T&H) integrated circuit that is able to sample an incoming high-speed PAM4 signal and feed it to an analog to digital converter (ADC). This building block acts as a front-end in optical transceivers carrying sensitive data, where power consumption and cost are a primary concern. The proposed architecture is discussed in detail and a design approach based on the switched capacitor architecture is examined and simulated. Parasitic based capacitance is utilized to hold the signal, and post-layout simulation shows a low power consumption of 42 mW while sampling a 1 GS/s PAM4 signal at 200 MSps (Mega-samples per second). Our circuit has a 10 times lower power consumption compared to a similar implementation in BiCMOS and a comparable power consumption to similar CMOS implementations but with a higher output voltage swing and far less smaller area. Our circuit is designed for PAM4 signals but can be used for NRZ as well, which is a first of its kind in sample and hold circuits targeting serial modulated signals such as PAM4. [ABSTRACT FROM AUTHOR]

Reduction of the crosstalk (CT) between contiguous photonic components is still a big challenge in fabricating high packing density photonic integrated circuits (PICs). Few techniques to accomplish that goal have been offered in recent years but all in the near-IR region. In this paper, we report a design for realizing a highly efficient CT reduction in the MIR regime, for the first time to the best of our knowledge. The reported structure is based on the silicon-on-calcium-fluoride (SOCF) platform with uniform Ge/Si strip arrays. Using Ge strips shows better CT reduction and longer coupling length (Lc) than the conventional Si based devices over a wide bandwidth in the MIR region. The effect of adding a different number of Ge and Si strips with different dimensions between two adjacent Si waveguides on the Lc and hence on the CT is analyzed using both full vectorial finite element method and 3D finite difference time domain method. An increase in the Lc by 4 orders of magnitude and 6.5 times are obtained using Ge and Si strips, respectively, compared to strips-free Si waveguides. Consequently, crosstalk suppression of − 35 dB and − 10 dB for the Ge and Si strips, respectively, is shown. The proposed structure is beneficial for high packing density nanophotonic devices in the MIR regime, such as switches, modulators, splitters, and wavelength division (de)multiplexers, which are important for MIR communication integrated circuits, spectrometers, and sensors. [ABSTRACT FROM AUTHOR]

This paper presents a theory for the power transfer efficiency of printed circuit board coils to integrated circuit coils, with focus on load-dependence for low-power single-chip systems. The theory is verified with electromagnetic simulations modelled on a 350 nm CMOS process which in turn are verified by measurements on manufactured integrated circuits. The power transfer efficiency is evaluated by on-chip rectification of a 151 MHz signal transmitted by a spiral coil on a printed circuit board at 10 mm of separation to an on-chip coil. Such an approach avoids the influence of off-chip parasitic elements such as bond wires, which would reduce the accuracy of the evaluation. It is found that there is a lower limit for the load below which reducing the power consumption of on-chip circuits yield no increase in voltage generated at the load. For the examined process technology, this limit appears to lie around 56 k Ω . The paper is focused on the analysis and verification of the theory behind this limit. We relate the results presented in this work to the application of wireless single-chip temperature monitoring of power semiconductors and conclude that such a system would be compatible with this limit. [ABSTRACT FROM AUTHOR]

In this paper, a new fundamental cell in positive feedback source coupled logic is presented, which is an improvement over the existing fundamental cell employed in digital circuit design in various high resolution mixed-signal integrated circuits. The operation of the existing fundamental cell relies on using large sized transistor in its centre branch, resulting in significantly larger implementation area. The proposed fundamental cell incorporates multi-threshold transistor in the center branch thereby allowing designer to use reduce its dimension and hence the area. The impact of the proposed modification is examined by configuring the cell as two input exclusive OR (XOR2) gate. The behaviour is analysed in terms of static and propagation delay parameters which are modelled and a design procedure is also elaborated. The theoretical prepositions are verified by designing and simulating for various operating conditions using model parameters of 180 nm CMOS technology node. A maximum error of 27% is observed between the simulated and predicted parameters. The process variation study through Monte Carlo analysis and PVT variations identifies the proposed fundamental cell based circuit as less prone to variations in comparison to existing fundamental cell based counterparts. A full adder, as an application of the proposed fundamental cell, shows a significant (66%) area reduction while delay, power and PDP are within 4% of their corresponding values for the existing one. [ABSTRACT FROM AUTHOR]

When the integrated circuit (IC) feature size is reduced to 0.13 μm and below, copper (Cu) becomes the new wiring material in interconnect materials. The double damascene process is the only process for Cu patterning that is mature and has been successfully applied to IC manufacturing, so Cu interconnection chemical–mechanical polishing (CMP), which can achieve the surface nanoscale accuracy required by lithography level, is of great importance to the IC industry. The slurry is the most important component of the CMP materials and has a significant impact on the surface quality of the polished wafer. Therefore, how to select suitable additives to improve the chemical effect and obtain excellent post-polishing surface and good slurry stability while saving cost is an urgent issue to be considered. The research progress of each component in Cu interconnection slurry was discussed in this paper, mainly focusing on the advantages and disadvantages of acidic and alkaline slurries, and the research progress of oxidants, complexing agents, surfactants, and corrosion inhibitors as well as their respective action mechanisms were analyzed in detail, which will be a great contribution to the IC field. It will facilitate the optimization of the slurry for further development of new Cu interconnection CMP slurry. [ABSTRACT FROM AUTHOR]

This paper presents a new systematic design of a grounded memristor emulator circuit. It uses only one active device, namely an operational transconductance amplifier, and one passive element, namely a capacitor. Moreover, the used capacitor is grounded, which is suitable for monolithic integration. The proposed memristor is simple in design and can be used for both incremental and decremental memristor emulators by changing a switch positions. An application of the proposed grounded memristor as a first-order high-pass filter is also realized. Furthermore, the comparison of the proposed memristor emulator with available literature has been included. The proposed memristor emulator provides the following advantageous features such as low active and passive component counts, resistorless, grounded capacitor suitable for monolithic integration, low power consumption, and small area. The obtained results are included which are verified on Cadence Virtuoso at 180-nm Generic Process Design Kit CMOS technology parameter. The proposed emulator occupies the (76.94)·(33.75) µm2 layout area excluding the capacitor. The pre-layout and post-layout simulation results of the memristor emulator are also presented. [ABSTRACT FROM AUTHOR]

As technology advances, circuit density and complexity increases in integrated circuits which make the devices vulnerable to different types of manufacturing defects. In such cases, even the occurrence of a fault may be critical. Hence, ensuring Static random access memory (SRAM) reliability and quality with high priority is essential. In this paper, an innovative approach to SRAM testing—wavelet-based transient supply current testing with modified March sequence exploiting read equivalent stress (RES) is introduced for fault detection. The main contribution of this research work is the unique testing solution that ensures a minimum test time for the detection of open defects in SRAMs. In comparison with other techniques that solely rely on the hardware implementation for fault detection, the proposed technique reduces design parameters, such as the area overhead, power consumption, hardware complexity and performance overhead. The simulation results demonstrate that the proposed technique can provide high reliability and efficiency and reduce test time (25%) compared to other methods. A complete evaluation of the proposed technique in terms of the overall memory performance is presented in this work. The main objective of this study is to investigate the efficiency of wavelet-based transient current test in detecting all open defects targeted in this work in SRAMs amidst process variations. Moreover, the conventional test time of transient current test is minimized exploiting the effects of RES. [ABSTRACT FROM AUTHOR]

A novel current mode charge-controlled grounded memristor emulator configuration has been reported in the paper, based on only one Arbel-Goldminz cell-operational transconductance amplifier and a single grounded capacitor. The proposed circuits employ only eight MOS transistors and possess a sisngle active component matching constraint, while the MOS-capacitance can be used instead of classical capacitance in a situation involving the simulator working within a high frequency range of up to 100 MHz, thereby offering obvious benefits in terms of implementation in the form of an integrated circuit. The proposed solution offers a variable switching mechanism—soft and hard—as well as the possibility of generating an inverting memristance characteristic, depending on the value of the frequency of the input current signal and the applied capacitance. For the verification purpose, PSPICE simulation environment with CMOS 0.18 um TSMC technology parameters has been selected. The experimental check was performed with commercial IC MAX435 component (an experimental test using off-the-shelf components), showing good agreement with theoretical assumptions. [ABSTRACT FROM AUTHOR]

This paper originality is put forward a second-generation voltage conveyor (VCII) based voltage-mode PID controller. The proposed circuit includes a single VCII-, two capacitors, two resistors, and no need any passive component matching conditions. The sensitivity has been investigated for the control parameters. Besides, the impacts on operating frequency ranges of the parasitic impedances have been examined. Simulation outcomes have been obtained by operating TSMC 0.18 μm CMOS technology parameters with power supply ± 0.9 V. Additionally, a closed-loop control system application is included to demonstrate the circuit's functioning. An experimental study is given to confirm the time-domain performance of the proposed circuit by using commercially available integrated circuits. [ABSTRACT FROM AUTHOR]

In the modern era, advances in CMOS technology have increased the number of transistors and the complexity of computations that can be performed on each chip. Due to the many limitations of this technology, to reduce the size of the chips to the nanotechnology level and to continue Moore's law, the unique properties of quantum cellular automata have made it a candidate for future integrated circuits. Operational units such as logic and arithmetic units are the main components of processors, among which the operation of addition and subtraction is the most widely used arithmetic operator, and the design of redundant ternary adder without publishing the carry affects the performance of processors. The main aim of this paper is to design a redundant full adder and full subtractor by employing a carry and borrow bit generator module based on ternary QCA (TQCA) innovation. Based on this, the block diagram structure of the ternary redundant adder/subtractor-based TQCA circuit is presented, which includes a proposed new carry/borrow generator gate based on TQCA. The proposed full adder design has 423 ternary cells, area 0.09 µm2 and cost 647.19, and the full subtractor has 431 ternary cells, area 0.09 µm2 and cost 710.7. For validation, the circuits were simulated with the TQCAsim software. The results of this innovation show that the proposed architecture has significant advantages. [ABSTRACT FROM AUTHOR]

Designing reliable Networks on Chip (NoCs) is critical, especially with the continuous scaling down of integrated circuit technology, which exposes NoCs to various types of faults. In this paper, a reliability-aware application mapping technique for improving the reliability of heterogeneous NoCs is proposed. It is based on a hybridization of the Multi-Objective Particle Swarp Optimization (MOPSO) algorithm and Reinforcement Learning (RL). At design time, MOPSO and RL perform the optimization of an initial mapping and the prediction of fault-tolerant remapping scenarios, respectively. To teach and to produce an intelligent agent capable of generating an optimal adaptive remapping scheme to address run-time permanent processing element (PE) failures. Two models of RL agents are trained, each based on a different mechanism of task migration: 1) step-based agent and 2) swap-based agent. Experiments were carried out to assess the performance of our innovative technique on various sizes of NoCs, using real benchmarks and varying the levels of heterogeneity and failure in the NoC. The results of the experiments reveal that using RL to solve the reliability problem in NoCs yields interesting results in terms of reliability, energy consumption, execution time, and cost migration. [ABSTRACT FROM AUTHOR]

Dielectric singularities (DSs) constitute one of the most exotic features occurring in the effective permittivity of artificial multilayers called hyperbolic metamaterials (HMMs). Associated to DSs, a rich phenomenology arises that justifies the ever-increasing interest profuse by the photonic community in achieving an active control of their properties. As an example, the possibility to "canalize" light down to the nanoscale as well as the capability of HMMs to interact with quantum emitters, placed in their proximity, enhancing their emission rate (Purcell effect), are worth mentioning. HMMs, however, suffer of an intrinsic lack of tunability of its DSs. Several architectures have been proposed to overcome this limit and, among them, the use of graphene outstands. Graphene-based HMMs recently shown outstanding canalization capabilities achieving λ/1660 light collimation. Despite the exceptional performances promised by these structures, stacking graphene/oxide multilayers is still an experimental challenge, especially envisioning electrical gating of all the graphene layers. In this paper, we propose a valid alternative in which indium-tin-oxide (ITO) is used as an electrically tunable metal. Here we have numerically designed and analyzed an ITO/SiO2 based HMM with a tunable canalization wavelength within the range between 1.57 and 2.74 μm. The structure feature light confinement of λ/8.8 (resolution of about 178 nm), self-focusing of the light down to 0.26 μm and Purcell factor of approximately 700. The proposed HMM nanoarchitecture could be potentially used in many applications, such as ultra-fast signal processing, high harmonic generation, lab-on-a-chip nanodevices, bulk plasmonic waveguides in integrated photonic circuits and laser diode collimators. [ABSTRACT FROM AUTHOR]

A new circuit realization of capacitance multiplier based on active block, current follower differential input transconductance amplifier is introduced in the paper. The circuit employs one current follower differential input transconductance amplifier, two resistors and one capacitor. The proposed capacitance multiplier has a good range of multiplication factor (up to 30). Multiplication factor of the proposed circuit is adjustable by external resistor and by bias current as well. The comprehensive study of the proposed circuit including non-idealities and parasitic element effects has been carried out. The proposed capacitance multiplier circuit is simulated on Cadence Virtuoso using 0.18 μm gpdk CMOS technology and post layout simulation results are demonstrated to validate the working of the proposed circuit. The layout of the used active block occupies an area of 26.26 μm × 28.79 μm. The proposed circuit shows good performance against transistors mismatch, process and temperature variations. Moreover, the experimental results of the circuit using off-the-shelf integrated circuits are also carried out to demonstrate its practicality. In the last, the transpose structure of the proposed capacitance multiplier circuit is also explored. The obtained transposed structure is realized using active element namely, voltage differencing buffered amplifier. [ABSTRACT FROM AUTHOR]

Materials with negative coefficients of thermal expansion (CTEs) can be used to prepare composites with specific CTE values. Negative thermal expansion behavior can be primarily attributed to two types of mechanisms: phase transition- and framework-type mechanisms. This paper reports Zr2SP2O12, which has unique negative thermal expansion behavior involving both mechanisms. Zr2SP2O12 undergoes a framework-type mechanism at temperatures <393 K or >453 K and an isosymmetric phase transition at 393–453 K. The volumetric CTE of α-Zr2SP2O12 is ~−70 p.p.m./K during the isosymmetric phase transition, and this value can be decreased by decreasing the proportion of sulfur. The minimum volumetric CTE of α-Zr2S0.9P2O12-δ is ~−108 p.p.m./K in the temperature range of 393–453 K. Between 303 and 773 K, the volume of α-Zr2S0.9P2O12 − δ is reduced by ~1.3%. Finally, this paper presents methods for the hydrothermal synthesis of α-Zr2SP2O12 and for controlling the sulfur content. Composites: More than one way to control overheating An unusual crystal that shrinks in response to heat can help avoid damage to composite materials, such as computer chip components, facing unexpected temperature changes. While most atoms tend to move apart as a crystal is warmed up, in negative thermal expansion materials the atoms move closer together. Toshihiro Isobe and colleagues from the Tokyo Institute of Technology in Japan report a method for synthesizing an oxide containing zirconium, sulfur, and phosphorus that exhibits two distinct mechanisms of negative thermal expansion. This oxide undergoes a crystal phase change that provides a large shrinking effect within a narrow temperature range. The crystal is capable of smaller contractions through a broader heating span through atomic framework rearrangements. These variable properties make it easier to fine-tune thermal expansion effects to meet specific applications. Zr2SP2O12 has unique negative thermal expansion behavior involving both phase transition- and framework-type mechanisms. The volumetric CTE of α-Zr2SP2O12 is approximately −70 ppm/K during the isosymmetric phase transition in the temperature range of 393–453 K. This value can be improved by decreasing the proportion of sulfur. The minimum volumetric CTE of α-Zr2S0.9P2O12-δ is approximately −108 ppm/K. [ABSTRACT FROM AUTHOR]

In the digital design area, quantum-dot cellular automata (QCA) has become a promising alternative to the CMOS technology. As a basic unit in digital arithmetic circuits, the full adder has been extensively studied in the development of QCA technology. This paper presents two novel full adder implementations using QCA, which outperform other designs with fewer cells, smaller areas, shorter latency and lower cost. The two full adders share many properties in common and differ only in cell numbers. Concretely speaking, a latency of 0.75 clock cycle, area of 0.01 μm2 and cost weighted 0.0056 is implemented using only 28 and 31 normal cells, respectively. To illustrate the superiority of our design in complex structures, ripple carry adder circuits of 4-bit, 8-bit and 16-bit size have been implemented using the proposed 1-bit full adder. Simulation results show that the proposed design also has good stability and scalability in different circuit size, resulting in significant improvements in terms of number of cells, area, cost compared to designs in other studies, while maintaining an equally well clock latency with the best previous one. The proposed designs in this paper have been functionally verified with the QCADesigner tool. [ABSTRACT FROM AUTHOR]

Understanding tool wear characteristics in machining SiC particle–reinforced aluminum matrix (SiCp/Al) composites is crucial for tool structure design and promising wide application of the material. This paper comprehensively studied the effect of particle volume fractions (PVFs) on the wear characteristics for the multi-coated cutting tool in turning SiCp/Al composites. Tool wear curves for machining SiCp/Al/15%p, 30%p, and 45%p were depicted. Importantly, the tool wear characteristics for full wear stages on rake and flank face were obtained for the first time. Results show that the increase of PVFs accelerated the removal of coating and the peeling of the adhesive layer. Different appearances of the adhesive wear on the rake face were found, where the deposited and adhesive layers were in turning SiCp/Al/15%p, and deposited layer and microchip adhesion were in turning SiCp/Al/30%p and 45%p. Specifically, strong protection of adhesive layer prevented the formation of coating shedding and crater wear on the rake face in turning SiCp/Al/15%p. The wear characteristics on the flank face were characterized by adhesive wear, abrasive wear, and coating shedding, which remained consistent whether in different PVFs or at different wear stages. [ABSTRACT FROM AUTHOR]

In this paper, through a systematic approach, four new very-low-frequency third-order quadrature sinusoidal oscillators (TOQSO), especially suitable for generating very low oscillation frequencies in the sub-audio range (< 20 Hz and further down), have been derived. Each of the four proposed TOQSOs employs three current feedback op-amps (CFOA), five resistors and three grounded capacitors, as preferred for integrated circuit (IC) implementation. All the oscillators provide independent control of the condition of oscillation (CO) and the frequency of oscillation (FO). The workability and utility of the proposed TOQSOs have been corroborated by simulation results and the hardware implementation results employing AD844-type IC CFOAs. [ABSTRACT FROM AUTHOR]

Object detection is one of the most challenging tasks in computer vision. With the advances in semiconductor devices and chip technology, hardware accelerators have been widely used. Field-programmable gate arrays (FPGAs) are a highly flexible hardware platform that allows customized reconfiguration of the integrated circuit, which has the potential to improve the efficiency of object detection accelerators. However, few reviews summarize FPGA-based object detection accelerators. Also, there is no general principle for realizing object detection according to FPGA characteristics. In this paper, the current hardware accelerators are introduced and compared. Then, the typical deep learning-based object detectors are summarized. Next, the questions of "Why choose FPGA," "The design goals of FPGA accelerators" and "The design methods for FPGA accelerators" are discussed in detail. Finally, the challenges of object detection algorithms, hardware, and co-design are presented. In addition, an online platform (https://github.com/vivian13maker/) is constructed to provide specific information on all advanced works. [ABSTRACT FROM AUTHOR]

Existing circuit camouflaging techniques to prevent reverse engineering increase circuit-complexity with significant area, energy, and delay penalty. In this paper, we propose an efficient hardware encryption technique with minimal complexity and overheads based on ferroelectric field-effect transistor (FeFET) active interconnects. By utilizing the threshold voltage programmability of the FeFETs, run-time reconfigurable inverter-buffer logic, utilizing two FeFETs and an inverter, is enabled. Judicious placement of the proposed logic makes it act as a hardware encryption key and enable encoding and decoding of the functional output without affecting the critical path timing delay. Additionally, a peripheral programming scheme for reconfigurable logic by reusing the existing scan chain logic is proposed, obviating the need for specialized programming logic and circuitry for keybit distribution. Our analysis shows an average encryption probability of 97.43% with an increase of 2.24%/ 3.67% delay for the most critical path/ sum of 100 critical paths delay for ISCAS85 benchmarks. Hardware security is importance with outsourcing of integrated circuit fabrication to various foundries. Here, the authors propose a compact encryption logic based on the active interconnects constructed with ferroelectric field-effect transistors. [ABSTRACT FROM AUTHOR]

This paper presents a charge controlling circuit technique to integrate a charge balancer circuitry in the output-stage of electrical neural stimulators with the aim to reduce the area and the power consumption of the charge balancing circuitry. The proposed architecture is an inter-pulse charge control technique that senses the electrode voltage and provides stable charge balancing throughout the entire stimulation parameters. To ensure the stability, only one side of the output stage is active during the charge balancing phase. The stimulator employed in the proposed system has an adaptive quad-rail compliance as high as 45 V, configurable from 5 to 45 V, according to the requirement of the application. Thanks to a straightforward structure of the proposed charge control circuit, the proposed charge balancer (CB) performs with low power consumption (from 3.5 to 14.8 μ W), occupies small silicon area (0.102 mm 2 ), and has a high dynamic-range of power supply compliance in comparison to similar existing consequence-based charge control blocks as well as performs charge balancing for a wider range of tissue impedance. According to its reported characteristics, the proposed method leads to an improvement in stability, power consumption, area and power supply compliance as well as tissue impedance range compared to the state-of-the-art charge balancing methods. [ABSTRACT FROM AUTHOR]

This paper proposes a circuit configuration to emulate the behaviour of a floating/grounded incremental/decremental flux-controlled meminductor, based on multiple output voltage differencing transconductance amplifier-MO-VDTA. The circuits use two grounded capacitors which benefit from the integrated circuit (the MOS-capacitance can be used instead of the capacitor when the simulator circuits are operated in the high frequency region) and has a single active component matching constraint. The influence of possible non-ideality and parasitic effects was analysed, while the effects of the parasitic are only marginal due to the absence of any passive elements. The designed circuit also possesses the electronic tunability feature, which supports the controllable nature of realized inverse meminductance. The applicability of the proposed emulator has also been shown in neural network applications. The emulation circuit has been verified by executing simulations using CMOS 0.18 μm process technique under SPICE environment. [ABSTRACT FROM AUTHOR]

This paper presents a comprehensive review of ambient RF energy harvester circuitry working on integrated circuits. The review covers 3 main blocks in an RF energy harvesting system implemented on chip. The blocks are the rectifier, impedance matching circuit and power management unit. The review of each block includes its operational principle, reported state-of-the-art circuit enhancement techniques, and design trade-offs. We compare the circuits in each block with respect to the techniques adopted to improve the performances for RF energy harvesting. To identify the benefits and limitations associated with the architecture we discuss the advantages and disadvantages of the circuit topologies in each block of an ambient RF energy harvester. [ABSTRACT FROM AUTHOR]