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In signal processing applications, the multipliers are essential component of arithmetic functional units in many applications, like digital signal processors, image/video processing, Machine Learning, Cryptography and Arithmetic & Logical units (ALU). In recent years, Profuse multipliers are there. In that, Vedic multiplier is one of the high-performance multiplications and it is used to signal/image processing applications. In order to ameliorate the performance of this multiplier further, by proposed a novel multiplier using hybrid compressor. The proposed hybrid compressor-based multiplier is designed and implemented in Field programmable Gate Array (FPGA—spartan 6). The synthesis result shows that the speed of proposed hybrid compressor-based multiplier gets improved as compared to Array multiplier (35.83%), Wallace tree multiplier (34.58%), Vedic Multiplier based on Carry look ahead adder (CLA) (28.49%), Vedic Multiplier based on Ripple carry adder (RCA) (20.65%), Booth Multiplication (21.65%) and Vedic Multiplication based on Han-Carlson Adder (HCA) (20.10%) and Hybrid multiplier using Carry Select Adder (CSELA) (17.81%) and Hybrid Vedic Multiplier (7.15%). [ABSTRACT FROM AUTHOR]

This paper proposes field programmable gate array (FPGA) realization of fuzzy PI controller for typical industrial process called stirred tank heater system. Due to the complex nature of fuzzy controller families, its implementation on digital signal processors (DSPs) result computational time delay which, in other words, makes the processing speed slower. To address the limitations of DSP implementation, an alternative digital hardware programmable device called FPGAs are being largely used for digital implementation of algorithms with higher computational speed and accuracy. The proposed work is inspired by this quality of FPGAs and aims to take advantage of reliable performance of fuzzy PI controllers with its complexity and having no considerable impact on processing speed. Here, fast and novel design approach for rapid prototyping of fuzzy PI controller for stirred tank heater is presented thoroughly. Xilinx system generator SIMULINK add on from VIVADO is used to generate very high-speed integrated circuit hardware description language (VHDL) directly from MATLAB. The developed controller for stirred tank system is verified in fixed point arithmetic using Xilinx Simulink blocks. The VHDL code is then generated, synthesized, implemented, and made ready for physical implementation on Kintex-7 evaluation board. [ABSTRACT FROM AUTHOR]

Square-root unscented Kalman filter (SRUKF) is a widely used state estimator for several state of-the-art, highly nonlinear, and critical applications. It improves the stability and numerical accuracy of the system compared to the non-square root formulation, the unscented Kalman filter (UKF). At the same time, SRUKF is less computationally intensive compared to UKF, making it suitable for portable and battery-powered applications. This paper proposes a low-complexity and power-efficient architecture design methodology for SRUKF presented with a use case of the simultaneous localization and mapping (SLAM) problem. Implementation results show that the proposed SRUKF methodology is highly stable and achieves higher accuracy than the extensively used extended Kalman filter and UKF when developed for highly critical nonlinear applications such as SLAM. The design is synthesized and implemented on resource constraint Zynq-7000 XC7Z020 FPGA-based Zedboard development kit and compared with the state-of-the-art Kalman filter-based FPGA designs. Synthesis results show that the architecture is highly stable and has significant computation savings in DSP cores and clock cycles. The power consumption was reduced by 64 % compared to the state-of-the-art UKF design methodology. ASIC design was synthesized using UMC 90-nm technology, and the results for on-chip area and power consumption results have been discussed. [ABSTRACT FROM AUTHOR]

Compared with off-line digital signal processing (DSP) verification, achieving the expected performance and hardware efficiency in application specific integrated circuit (ASIC) is more critical for DSP to reduce power consumption and cost. The performance of traditional frequency offset compensation algorithms based on feedforward structure is strongly dependent on the accuracy of frequency offset estimation. Therefore, frequency offset calculation and loop filtering implemented in ASIC or field programmable gate array (FPGA) usually choose high word-width fixed-point or floating-point operations, which increase the consumption of logical resources and reduce the clock frequency that hardware logic can achieve. This work proposes a frequency offset compensation scheme based on polar coordinate processing and feedback structure, and a pre-decision-based angle differential estimator is used to estimate the residual frequency offset. In the proposed feedback structure, the frequency offset estimator is realized by a simple accumulator, and the input of the accumulator is the residual frequency offset or its scaling, which will reduce the requirement for the accuracy of the residual frequency offset estimator. The offline verification results show that the performance of the proposed algorithm is close to that of the traditional algorithm, but the proposed algorithm has lower logic resource consumption and higher clock frequency in hardware implementation based on FPGA. The performance of the proposed method is evaluated in real-time through 10-Gbps data rate polarization-multiplexed quadrature phase shift keying modulation after 20-km standard single-mode fiber transmission. Compared with offline processing in MATLAB®, no hardware implementation penalty is observed. [ABSTRACT FROM AUTHOR]

The Xilinx ZCU111 Radio Frequency System on Chip (RFSoC) is a promising solution for reading out large arrays of microwave kinetic inductance detectors (MKIDs). The board boasts eight on-chip 12-bit / 4.096 giga samples-per-second (GSPS) analogue-to-digital converters (ADCs) and eight 14-bit / 6.554 GSPS digital-to-analogue converters (DACs), as well as field programmable gate array (FPGA) resources of 930,000 logic cells and 4,272 digital signal processing (DSP) slices. While this is sufficient data converter bandwidth for the readout of 8,000 MKIDs, with a 2 MHz channel-spacing and a 1 MHz sampling rate (per channel), additional FPGA resources are required to perform the DSP needed to process this large number of MKIDs, due to a mismatch between the data converter bandwidth relative to the FPGA resources of the ZCU111. A solution to this problem is the new Xilinx RFSoC 2x2 board. This board costs only one fifth of the ZCU111 while still providing the same logic resources, albeit with only a quarter of the data converter resources. Thus, using multiple RFSoC 2x2 boards would provide a better balance between FPGA resources and data converters, allowing the full utilization of the RF bandwidth provided by the data converters, while also lowering the cost per pixel value of the readout system; from approximately €2.50 per pixel with the ZCU111 to €1 per pixel with the 2x2. [ABSTRACT FROM AUTHOR]

Δ Σ analog-to-digital converters (ADCs) are largely used in sensor acquisition applications. In the last few years, standalone Δ Σ modulators have become increasingly available as off-the-shelf parts. To build a complete ADC, a standalone modulator has to be paired with some advanced elaboration unit, such as a field programmable gate array (FPGA) or a digital signal processor (DSP), which is needed for the implementation of the decimation filter. This work investigates the use of low-cost, general-purpose microcontrollers for the decimation of Δ Σ -modulated signals. The main challenge is given by the clock frequency of the modulator, which can be in the range of a few MHz . The proposed technique deals with this limitation by employing two serial peripheral interface (SPI) modules in a time-interleaved configuration. This approach allows for continuous acquisition and elaboration of relatively high-speed, digital signals. The technique has been applied to a case study, and a data conversion system has been practically realized. The performance of the proposed filter is compared to that of a digital filter, present on board a commercial microcontroller, and the results of experimental tests are provided. [ABSTRACT FROM AUTHOR]

Recent developments in power electronics technologies have resulted in a need for fast responses and dynamic control. However, existing control schemes are still limited to the available digital signal processors (DSPs) and their associated high prices. The field-programmable gate array (FPGA) offers fast performance and high control flexibility by providing a reconfigurable computing speed. However, it has some implementation limitations in standalone systems. In this regard, this paper presents a hardware setup for a three-level hybrid active neutral point inverter (HANPC) using a FPGA and a DSP. A unique method using digital and analog modulation is designed in this study using Vivado software. The proposed method depends on receiving analog reference signals from the DSP and then performing all the required processes using the FPGA. Direct pulse width modulation is generated to control the HANPC without changing the hardware configuration of the main topology. The implemented hardware is based on a 15 kW HANPC topology that is mainly controlled by a Digilent Zybo-Z7-20 FPGA. The effectiveness of the proposed system was verified by experimental results. [ABSTRACT FROM AUTHOR]

The reversible computation is the process of designing the architecture with reversible logic gates (RLG) and applicable for optical computing, digital signal processing, nanotechnologies and low-power circuits. In this study, integer wavelet transform (IWT) compression technique is applied to the input image to compress the pixel value. The utilization of the IWT is used to improve the quality of the image in terms of peak signal-to-noise ratio (PSNR) and structural similarity index matrix (SSIM). In addition, different types of RLGs are used to perform the encryption and decryption of the images. A random number is generated using the Lorenz chaotic system (LCS) that contains three different stages and each stage is developed using arithmetic blocks. Here, an effective key value is generated from the input image values by connecting the LCS's output with the heterogeneous key generation (HKG) module. The inverse IWT (IIWT) technique is used to retrieve the original data during execution of decryption operation. Application specific integrated circuit and field-programmable gate array (FPGA) performances are calculated for reversible logic cryptographic design (RLCD) IWT-HKG architecture. The results showed that it has achieved better performance compared to conventional methods. Moreover, security analyses such as avalanche effect, side channel attack and session key agreement are performed for the RLCD-IWT-HKG method. The RLCD-IWT-HKG method has achieved 89 LUTs, 52 flip flops and 31 slices for the Virtex 6 FPGA device. After retrieving the decrypted images, values of PSNR and SSIM are evaluated as 39.90 dB and 0.6874, respectively. [ABSTRACT FROM AUTHOR]

Improving the visibility of hazy images is desirable for robot navigation, security surveillance, and other computer vision applications. The presence of fog significantly damages the quality of the captured image, which does not only affect the reliability of the surveillance system but also produce potential danger. Therefore, developing as well as implementing a simple and efficient image de-hazing algorithm is essential. The reconfigurable computing devices like Field Programmable Gate Array and Digital Signal Processing (DSP) processors are used to implement these image processing applications. Several strategies are available for configuring these reconfigurable devices. In this paper, two approaches for hardware implementation of image de-hazing algorithm are presented. The pixel wise and gray image-based de-hazing algorithm is proposed in this paper. The key advantage of this proposed method is to estimate accurate transmission map. It eliminates the computationally complex step of refine transmission map as well as halos & artifacts in the recovered image and achieves faster execution without noticeable degradation of the quality of the de-hazed image. The proposed method is initially verified in MATLAB and compared with the existing four state-of-art methods. This algorithm is implemented on two different hardware platforms, i.e., DSP Processor (TMS320C6748) with floating pointing operations and Zynq-706 fixed-point operations. The performance comparison of hardware architectures is made with respect to Average Contrast of the Output Image, Mean Square Error, Peak Signal to Noise Ratio, Percentage of Haze Improvement and Structural Similarity Index (SSIM). The results obtained show that Zynq-706-based hardware implementation processing speed is 1.33 times faster when compared to DSP processor-based implementation for an image dimensions of 256 × 256 . [ABSTRACT FROM AUTHOR]

Efficient utilization of on-chip Static Random Access Memory (SRAM) space is more important on processor core design in modern Field Programmable Gate Array (FPGA) based Digital Signal Processing (DSP) applications. In the proposed High-performance Approximate Single Port (HASP) SRAM architecture, a significant amount of data is stored to achieve high performance. The constraints involved with high performance are counterbalanced to provide high accuracy, high speed, low power and area efficiency. In the proposed High-performance Approximate Sub-Bank Dual Port (HASBDP1 and HASBDP2) memory architectures, HASP has been employed and modified to work as a True DP SRAM with energy and area efficiency. The performance of the proposed memories is investigated by comparing its speed, area and power with those of the existing approaches. The proposed HASP SRAM provides 14.99% less power consumption and thirteen numbers of logic elements savings in the resource utilization than the existing conventional SP SRAM. By considering the design metrics, the proposed HASBDP SRAMs outperform than the conventional TDP and sub-bank DP SRAMs approaches. The proposed HASBDP2 exhibits 29.09%, 22.37% higher PSNR and 32.94%, 28.48% higher SSIM than the truncated least significant bit and static segment on-chip approximate memories respectively. [ABSTRACT FROM AUTHOR]

Digital signal processing besides multimedia applications needs plenty of data, real-time processing capacity, and high computational power. Thus, adaptable architectures with run-time reconfiguration abilities have gotten expanded consideration. Basically, Reconfiguration computing is going towards advancing the application adaptability at runtime. A reconfigurable structure can be attained by working up the strategy aimed at configuring an array of programmable logic reprogramming. Field Programmable Gate Arrays (FPGAs) is made with the intention of reconfiguring the array system with interconnects as well as the configuration of logic blocks. To implement a high-performance FPGA device and also to enhance, the given paper proposes a proficient design strategy. The proposed strategy count upon the employment of dynamic partial reconfiguration (DPR) to drive from one mode then onto the next utilizing time-multiplexing on the same chip region. Furthermore, reconfigure modules to spare considerable area and enable the low-cost FPGAs usage. In the given work, reconfigurations of the modules accompanied by the memory are finished. The DPR is implemented betwixt these modes to shift from one mode then onto the next. The proposed method helps in diverse applications with various demands and also attains high performance, power consumption together with throughput. The proposed work gives improved performance with fewer powers and less area utilization which is illustrated by the Experimental outcomes. [ABSTRACT FROM AUTHOR]

Online arithmetic operators offer advantages of reduction in resource utilization and interconnection complexity besides providing pipelining at digit level. Multiplierless constant coefficient multiplication using the shift-and-add technique is widely used in digital signal processing applications. This paper proposes a novel bit serial adaptation of the parallel shift-and-add algorithm to online arithmetic. The proposed multipliers use right shifts instead of the traditional left shifts resulting in causal online implementations. Graph-based and hybrid algorithms are developed for the estimation of the distance of a constant from a set of constants in terms of the number of additions and for the synthesis of online multiple constant multipliers under area and online delay constraints. The computational complexity of the algorithms is determined. Results of implementation on randomly generated constant sets and FIR filter instances show substantial improvements in the number of operations required using the distance heuristic. Further, it is shown that the proposed techniques and algorithms result in significant savings in resource utilization, logic depth, and clock frequency compared to parallel and digit-serial algorithms. [ABSTRACT FROM AUTHOR]

An FPGA-based acoustic time-delay meter with the post-detection correlation processing of pseudo-noise signals is proposed. The measurement method is based on the real-time computation of the mutual correlation function between the reference signal that follows the modulation law and the received signal. The experimental results obtained using a prototype of the developed system are presented. The results validated the viability of the developed software and hardware solutions as applied to acoustic-, radio-, and hydroacoustic-location systems. [ABSTRACT FROM AUTHOR]

A data-stream converter makes it possible to connect a radio telescope with wideband (512 MHz) signal-recording channels to active very-long-baseline interferometers using multichannel recording systems for narrowband (16 or 8 MHz) signals. A digital converter based on a field programmed gate array (FPGA) selects and formats up to 16 narrowband signals. [ABSTRACT FROM AUTHOR]

An online multi-component AM-FM signal decomposition method is proposed based on pre-filtered phase-locking scheme. A second-order generalized integrator (SOGI) and cascaded delayed signal cancelation technique (CDSC) are employed as pre-filters for the phase-locking scheme (PLL). The CDSC technique separates the AM-FM signals from the multi-component signal as a mono-component AM-FM, and a PLL structure demodulates the instantaneous amplitude (IA) and instantaneous frequency (IF) from the individual AM-FM signals. The IF estimated from PLL is fed back to SOGI and CDSC blocks in order to adaptively adjust the number of samples. PLL structures are augmented in parallel to extract IA and IF of multi-component AM-FM signals. The proposed scheme is implemented in field programmable gate array and tested for sinusoidal multi-component AM-FM model. It is evident from the simulation and experimental investigation that the algorithm could efficiently track IF and IA and offers good dynamic response and operating range. [ABSTRACT FROM AUTHOR]

Vector-controlled induction motor drives are quite popular in the industry in applications that demand high dynamic performance. This paper describes the implementation of a complete industrial vector-controlled drive for a 30 kW induction motor. The control algorithms for the drive are implemented using a TMS320F28335 Digital Signal Controller (DSC). Various monitoring and protection functions for the drive are implemented using a Cyclone IV FPGA that communicates with the DSC, and acts as the master controller for the drive. The FPGA also communicates with a Human-Machine Interface to provide a simple graphical control interface to the operator. [ABSTRACT FROM AUTHOR]

This paper describes the implementation on field programmable gate array (FPGA) of a turbo decoder for 3GPP Long-Term Evolution standard. Considering the high data rates required by this standard, parallel decoding architecture is used. The parallel decoding latency is reduced N times compared with the serial decoding latency, N being the parallelization factor, usually a power of 2. The decoding performances are similar for both serial and parallel schemes, when very low decoding latency is added to this theoretical parallel latency value. Taking advantage of the quadratic permutation polynomial interleaver properties, and considering some specific FPGA block memory characteristics, a novel simplified parallel decoding scheme is proposed, including only one interleaver, independently of the N value. Moreover, for the single interleaver, we propose a solution that exploits key arithmetic properties of the corresponding equation to perform the address computation in a recursive manner. The proposed method replaces divisions and multiplications by comparisons and subtractions. In addition, an even-odd merge sorting network provides correct data to all N decoding units. [ABSTRACT FROM AUTHOR]

Chrestenson generalized Walsh transform factorizations for parallel processing imbedded implementations on field programmable gate arrays are presented. This general base transform, sometimes referred to as the Discrete Chrestenson transform, has received special attention in recent years. In fact, the Discrete Fourier transform and Walsh-Hadamard transform are but special cases of the Chrestenson generalized Walsh transform. Rotations of a base- p hypercube, where p is an arbitrary integer, are shown to produce dynamic contention-free memory allocation, in processor architecture. The approach is illustrated by factorizations involving the processing of matrices of the transform which are function of four variables. Parallel operations are implemented matrix multiplications. Each matrix, of dimension N × N, where N = p , n integer, has a structure that depends on a variable parameter k that denotes the iteration number in the factorization process. The level of parallelism, in the form of M = p processors can be chosen arbitrarily by varying m between zero to its maximum value of n − 1. The result is an equation describing the generalised parallelism factorization as a function of the four variables n, p, k and m. Applications of the approach are shown in relation to configuring field programmable gate arrays for digital signal processing applications. [ABSTRACT FROM AUTHOR]

In our previous work, we presented a brief analysis of the performance of the code block segmentation procedure adopted by the 3GPP LTE Advanced (LTE-A) Standard as part of its physical layer channel coding scheme. Here, a detailed analysis of its performance is offered along with a new approach to the LTE-A code block segmentation procedure. Code block segmentation is a generic procedure applied before turbo encoding whose function is to fragment a large transport block (TB) into smaller code blocks, reducing the decoding latency of turbo decoders (Sun et al. in Integr VLSI J 44(4):305-315, ). Analysis showed that only 39 % of all TBs need segmentation. Results based on two different architectures, one focused on a digital signal processors and the other on an field programmable gate array are compared and discussed. A new approach for code block segmentation is presented. This new approach exhibits a speed up of more than 83 times over previous and new approaches presented here. [ABSTRACT FROM AUTHOR]

Digital signal processor (DSP) and field programmable gate array (FPGA) based concentrated control systems are designed for implementing CPS-SPWM strategies. The self-defined universal asynchronous receiver/transmitter (UART) protocol is used for communication between a master controller and an individual module controller via high speed links. Aimed at undesired pulse competition, this paper analyzes its generation mechanism and presents a new method for eliminating competition pulses with no time delay. Finally, the proposed concentrated controller is applied to a 10kV/10MVar distribution static synchronous compensator (DSTATCOM) industrial prototype. Experimental results show the accuracy and reliability of the concentrated controller, and verify the superiority of the proposed elimination method for competition pulses. [ABSTRACT FROM AUTHOR]

This work describes the design, implementation, and performance evaluation of an orthogonal frequency division multiple access (OFDMA) time-division duplexing (TDD) physical layer (PHY) compliant with the worldwide interoperability for microwave access (WiMAX) standard using a costeffective software-defined radio (SDR) platform containing field programmable gate array (FPGA) and digital signal processor (DSP) modules. We show that the proposed SDR architecture is capable of supporting the wide variety of configuration options described in the WiMAX standard while fulfilling the stringent requirements of WiMAX OFDMA TDD PHYs. The architecture allows for the implementation of all TDD functionalities in the downlink and the uplink at both the base station and the mobile station. The proposed design is shown to efficiently use the available FPGA and DSP resources. We also carried out specific experiments that take into account the frame and the downlink map messages detection over ITU-R wireless channel models to illustrate the performance of the proposed design. Finally, we discuss the utilization of the proposed hardware architecture to implement the wirelessMAN-advanced air interface. [ABSTRACT FROM AUTHOR]

This paper presents the design of a field-programmable gate array (FPGA)-based motion controller for robotic applications. In contrast to digital signal processor and microprocessor implementations, the control period of this system is fixed. Foregoing implementations on FPGA require microprocessor-based platforms for data interchange tasks consuming a large amount of resources; consequently, they could not be implemented on low logic density devices, or they use IP cores which limits the implementation of the system to only certain device families. This new motion controller architecture integrates control and communication modules in a single chip which permits an increase to the number of axis according to the system requirements. The proposed design presents a low consumption of logic resources; therefore, a considerable cost saving per axis is achieved. The system test has been carried out with a three-degree of freedom selective compliant assembly robot arm robot and a standard PC as master device. The digital filter parameters have been tuned by using a crossover frequency method. Step and profiled motion responses obtained show very good performance. [ABSTRACT FROM AUTHOR]

Recent research has shown that field programmable gate arrays (FPGAs) have a large potential for accelerating demanding applications, such as high performance digital signal process applications with low-volume market. The loss of generality in the architecture is one disadvantage of using FPGAs, however, the reconfigurability of FPGAs allow reprogramming for other applications. Therefore, a uniform FPGA-based architecture, an efficient programming model, and a simple mapping method are paramount for the wide acceptance of FPGA technology. This paper presents MASALA, a dynamically reconfigurable FPGA-based accelerator for parallel programs written in thread-intensive and explicit memory management (TEMM) programming models. Our system uses a TEMM programming model to parallelize demanding applications, including application decomposition into separate thread blocks and compute and data load/store decoupling. Hardware engines are included into MASALA using partial dynamic reconfiguration modules, each of which encapsulates a thread process engine that implements the hardware's thread functionality. A data dispatching scheme is also included in MASALA to enable the explicit communication of multiple memory hierarchies such as interhardware engines, host processors, and hardware engines. Finally, this paper illustrates a multi-FPGA prototype system of the presented architecture: MASALA-SX. A large synthetic aperture radar image formatting experiment shows that MASALA's architecture facilitates the construction of a TEMM program accelerator by providing greater performance and less power consumption than current CPU platforms, without sacrificing programmability, flexibility, and scalability. [ABSTRACT FROM AUTHOR]

The 2D Discrete Wavelet Transform (DWT) is an important function in many multimedia applications, such as JPEG2000 and MPEG-4 standards, digital watermarking, and content-based multimedia information retrieval systems. The 2D DWT is computationally intensive than other functions, for instance, in the JPEG2000 standard. Therefore, different architectures have been proposed to process 2D DWT. The goal of this paper is to review and to evaluate different algorithms and different kinds of architectures such as application-specific integrated circuits, field programmable gate array, digital signal processors, graphics processing units, and General-Purpose Processors (GPPs) that are used to process 2D DWT. In addition, we implement the 2D DWT using different algorithms on GPPs enhanced with multimedia extensions. The experimental results show that the largest speedup of the vectorized 2D DWT over the scalar implementation is about 2.8 for first level decomposition. Furthermore, the characteristics of the 2D DWT and disadvantages of the existing architectures such as GPPs enhanced with SIMD instructions are discussed. [ABSTRACT FROM AUTHOR]

Parameter interpolation is more capable of modern computer numerical control (CNC) than traditional linear/circular interpolation with higher speed and higher precision. Most of non-uniform rational B-spline (NURBS) interpolation algorithms were developed based on the chord error and machines capability, where interpolation points are calculated beforehand to overcome acceleration/deceleration (acc/dec) and jerk problem, which needs large memory. In this paper, a NURBS interpolator based on feedrate section is proposed. Instead of a single interpolation point, this interpolator aims to feedrate section, which makes it possible to run on a digital signal processor or field programmable gate array (FPGA) whose memory is limited. Experiment on FPGA showed the performance of interpolation. A mould experiment verifies the feasibility of application. [ABSTRACT FROM AUTHOR]

low-complexity high performance Rayleigh fading simulator, and its Field Programmable Gate Array (FPGA) implementation are presented. This proposed method is a variant of the method of filtering of the white Gaussian noise where the filter design is accomplished in the analog domain and transferred into digital domain. The proposed model is compared with improved Jakes' model, auto-regressive (AR) filtering, existing auto-regressive moving-average (ARMA) filtering techniques, and inverse discrete Fourier transform (IDFT)-based techniques, in performance and computational complexity. The proposed method outperforms AR(20) filter and modified Jakes' generators in performance. Although IDFT method achieves the best performance, it brings a significant cost in storage. The proposed method achieves high performance with the lowest complexity, and its performance has been verified on commercially available FPGA platforms. Our fixed-point Rayleigh fading-channel emulator uses only 2% of the configurable slices, 1% of the Look-Up-Table (LUT) resources and 3% of the dedicated multipliers on the FPGA platform that has been used. [ABSTRACT FROM AUTHOR]

Tool condition monitoring is a major problem that must be handled in order to detect and prevent failures in machine tools. Most modern rotating machines have a servo driver whence it is possible to acquire without sensors a current signal which is associated with cutting forces and cutting tool condition. This paper presents a hardware signal processing unit implemented in a field programmable gate array to acquire and condition signals from several machining processes. The system has been tested in both industrial and laboratory processes, producing satisfactory results. The design is reconfigurable in situ, since a few internal registers are programmed dynamically without recompilation which allows the same unit to be applied in different processes; the content of this memory is a set of filter coefficients. This implementation guarantees an inexpensive stand-alone unit since it does not require computers or microprocessors to process signals from different machinery as preparation for further processing. [ABSTRACT FROM AUTHOR]

A new method is proposed to achieve a multirate overlapped code division multiple access system (OV-CDMA) based on a novel code overlapping procedure. The signal-to-interference ratio (SIR) performance has been investigated for such system. A channel model that allows multirate overlapped transmission is presented based on which a closed form solution for the SIR has been derived. In addition, a simple yet very efficient block diagram of the transmitter and the receiver architecture has been proposed for such a system. Based on the proposed block diagram, the encoder-decoder has been implemented using an FPGA. Numerical results show that the newly proposed OV-CDMA scheme outperforms the classical variable processing gain fast frequency hopping CDMA (VPG-FFH-CDMA) for different system scenarios. Finally, real-time measurements have been successfully obtained using a hardware prototype utilizing the simple Xilinx Spartan IIE (XC2S200E) FPGA. [ABSTRACT FROM AUTHOR]

The processing requirements for high speed data communication systems (symbol rates in excess of 5 MHz) are beyond the capabilities of programmable devices such as DSP chips and FPGAs. Designers of such systems have traditionally incurred the high none recurring engineering (NRE) costs and long development times associated with custom ASIC implementations. In this paper we highlight an emerging trend in the development of parametrizable, high speed datapaths for application in data communications. Such circuits can deliver the high throughputs associated with traditional ASIC implementations while at the same time provide the user with the ability to vary key system parameters, or even redefine the circuit functionality among a finite number of alternatives. They have the potential to significantly reduce the cost of implementing high-speed data communication systems by reducing the NRE costs. Moreover, the ability to use the same piece of hardware in a large number of different systems provides further price reductions due to economies of scale. In order to bring out key concepts associated with the design of such systems, the paper provides an in-depth description of three sample circuits. They are: (a) A versatile rake-receiver architecture for use in DSSS-CDMA based systems; (b) A highly reconfigurable baseband processing engine for application in a host of systems based on single carrier modulation; and (c) A highly versatile beamforming IC. [ABSTRACT FROM AUTHOR]

Interference cancellation techniques for direct-sequence code division multiple access (DS-CDMA) systems have the potential to provide significant capacity gains over conventional matched filter receivers. The complexity of the signal processing algorithms for interference cancellation often requires processing speeds that are beyond that of current digital signal processor (DSP) technology. In this paper, we show that this difficulty can be overcome by partitioning the algorithmic functionality into two core technologies (field programmable gate arrays [FPGA] and DSP devices) based on processing speed requirements. We give implementation proofs via a testbed that allows a dynamic reconfiguration among constituent receivers being considered. Experimental results on the performance of the receivers are presented. [ABSTRACT FROM AUTHOR]

This paper presents the design and implementation of a 16-bit sigma-delta digital to analog converter (DAC) for audio applications. In order to achieve high-order noise shaping without the stability problem inherent in the design of higher order loop, cascade structure may be used. One of the drawbacks in a multi-bit cascaded sigma delta modulator is the un-cancelled noise and the nonlinearity error. The idea of the proposed architecture is to present an improved version of cascaded multi-bit sigma-delta modulator to overcome these problems. Simulation results verify the superiority of the proposed modulator. Sampling rate conversion plays a predominant role in the signal processing and has a strong influence on the overall complexity and cost of efficient sigma-delta DAC. In this paper a technique to examine filter architectures that can be effectively applied in the interpolator design is also presented; the sigma-delta modulator design is implemented on a field programmable gate array (FPGA) for verification purpose and results are presented. [ABSTRACT FROM AUTHOR]