Search

Emerging spectrum trends require a higher integration of 5G New Radio Frequency Range 1 (FR1) and Frequency Range 2 (FR2) bands to enhance the availability of spectrum and spectrum-sharing opportunities. To enable the reception of both FR1 and FR2 bands in a seamless hardware entity, we propose combining homodyne and heterodyne architectures. This necessitates the incorporation of a down-converter module that transfers the incoming signals from FR2 bands down to FR1, ensuring compatibility with an FR1 direct-conversion receiver (DCR) for the final signal reception. The primary focus of this paper is the design and implementation of the required integrated down-converter. The module includes an integrated balun, a low-noise amplifier (LNA) with a bypass mode, a dual-mode mixer, and an intermediate frequency (IF) amplifier. The introduced bypass mode helps to further elevate the linearity performance compared to the nominal mode. The bypass mode is designed for joint communication and sensing operation to avoid the compression of the receiver. This work also incorporates a local oscillator (LO) signal distribution network with phase tuning elements using a mixed-signal approach. The circuit is implemented in a 22-nm CMOS process, and the active die area is 0.6 mm 2 . The measurements demonstrate that the implemented chip can efficiently perform the required frequency conversion over a wide frequency range of 18–28 GHz. Conversion gain of 4.5–7.5 dB, noise figure of 15–19.7 dB, 1 dB compression point (IP1dB) of − 16 to − 10 dBm, and input third-order intercept point (IIP3) of − 5 to 0 dBm are achieved. The measured IP1 dB and IIP3 for the bypass mode are +0.5 to +4.5 dBm and +8.5 to +10 dBm, respectively. [ABSTRACT FROM AUTHOR]

In this paper, we present a high data rate implementation of a digital predistortion (DPD) algorithm on a modern mobile multicore CPU containing an on-chip GPU. The proposed implementation is capable of running in real-time, thanks to the execution of the predistortion stage inside the GPU, and the execution of the learning stage on a separate CPU core. This configuration, combined with the low complexity DPD design, allows for more than 400 Msamples/s sample rates. This is sufficient for satisfying 5G new radio (NR) base station radio transmission specifications in the sub-6 GHz bands, where signal bandwidths up to 100 MHz are specified. The linearization performance is validated with RF measurements on two base station power amplifiers at 3.7 GHz, showing that the 5G NR downlink emission requirements are satisfied. [ABSTRACT FROM AUTHOR]

The nonlinearities of power amplifiers combined with non-contiguous transmissions found in modern, frequency-agile, wireless standards create undesirable spurious emissions through the nearby spectrum of data carriers. Digital predistortion (DPD) is an effective way of combating spurious emission violations without the need for a significant power reduction in the transmitter leading to better power efficiency and network coverage. In this paper, an iterative, multi sub-band version of the sub-band DPD, proposed earlier by the authors, is presented. The DPD learning is iterated over intermodulation distortion (IMD) sub-bands until a satisfactory performance is achieved for each of them. A sequential DPD learning procedure is also presented to reduce the hardware complexity when higher order nonlinearities are incorporated in the DPD learning. Improvements in the convergence speed of the adaptive DPD learning are also achieved via incorporating a variable learning rate and interpolation of previously trained DPD coefficients. A WARPLab implementation of the proposed DPD is also shown with excellent suppression of the targeted spurious emissions. [ABSTRACT FROM AUTHOR]

Digital predistortion (DPD) is a widely adopted baseband processing technique in current radio transmitters. While DPD can effectively suppress unwanted spurious spectrum emissions stemming from imperfections of analog RF and baseband electronics, it also introduces extra processing complexity and poses challenges on efficient and flexible implementations, especially for mobile cellular transmitters, considering their limited computing power compared to basestations. In this paper, we present high data rate implementations of broadband DPD on modern embedded processors, such as mobile GPU and multicore CPU, by taking advantage of emerging parallel computing techniques for exploiting their computing resources. We further verify the suppression effect of DPD experimentally on real radio hardware platforms. Performance evaluation results of our DPD design demonstrate the high efficacy of modern general purpose mobile processors on accelerating DPD processing for a mobile transmitter. [ABSTRACT FROM AUTHOR]

This paper presents a novel digital self-interference canceller for an inband multiple-input-multiple-output (MIMO) full-duplex radio. The signal model utilized by the canceller is capable of modeling the in-phase quadrature (IQ) imbalance, the nonlinearity of the transmitter power amplifier, and the crosstalk between the transmitters, thereby being the most comprehensive signal model presented thus far within the full-duplex literature. Furthermore, it is also shown to be valid for various different radio frequency (RF) cancellation solutions. In addition to this, a novel complexity reduction scheme for the digital canceller is also presented. It is based on the widely known principal component analysis, which is used to generate a transformation matrix for controlling the number of parameters in the canceller. Extensive waveform simulations are then carried out, and the obtained results confirm the high performance of the proposed digital canceller under various circuit imperfections. The complexity reduction scheme is also shown to be capable of removing up to 65% of the parameters in the digital canceller, thereby significantly reducing its computational requirements. [ABSTRACT FROM AUTHOR]

A novel adaptive compensation architecture for the frequency response mismatch of 2-channel time-interleaved ADC (TI-ADC) is proposed for developing high-performance self-adaptive systems. The proposed approach overcomes the existing methods in the sense that the TI-ADC mismatch identification can be performed without allocating a region where only the TI-ADC mismatch spurs are present. This is accomplished via mapping the TI-ADC problem into an I/Q mismatch problem which allows deploying complex statistical signal processing. As proof of concept, the compensation architecture is demonstrated and tested on a 16-bit TI-ADC measured hardware data. [ABSTRACT FROM AUTHOR]