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Paper present possibility of creation a neuromatrix in the form crossbar architecture on a silicon substrate is shown. Crossbar architecture in the form of a set of nanosized conductors, between which there is a layer of titanium oxide, capable of changing its conductivity under the action of the applied voltage, it is proposed to form using the metho d of local anodic oxidation. The results is present of the study technological parameters of the metho d of local anodic oxidation silicon and titanium for the implementation of the elements of this neuromatrix in the form of a memristor structures. [ABSTRACT FROM AUTHOR]

Although digital processors offer high computing accuracy, they suffer enormously from lengthy execution times and high energy consumption as a result of the numerous communications between the processors and storage units. The disadvantage is especially acute when performing data-intensive operations, such as deep neural networks and matrix operations. To address this, several novel ideas and devices for implementing in-memory computing have been proposed. One of them is the memristor. Because of their scalability, nonvolatility, and analog storage characteristics, memristors have considerable potential and have achieved some encouraging research results. An eigenpair estimation method and a memristor-based crossbar structure are presented in this paper. The method differs from conventional computers in that the execution is carried out with the least number of controls and data transfers as possible. Almost all of the desired outcomes can be attributed to fundamental physical laws, such as Ohm's law and Kirchhoff's law. This method is then applied to principal component analysis (PCA) in the end. [ABSTRACT FROM AUTHOR]

An oscillatory process of a rod system of arbitrary shape is considered in the course of impact interaction with a falling load. The system may consist of a large number of rods rigidly or hingedly connected to each other, the impact occurring on one of the rod elements, thus causing a complex oscillatory process. As an example, vibrations of a rigidly embedded statically indeterminate flat twin-pillar frame are simulated, which experiences a drop of a load of a given mass and pre-shock velocity. One of the vertical frame legs has an initial curvature, the presence of which affects the maximum amplitude of transverse vibrations that occur during impact. The impact of the load on the frame crossbar is modeled taking into account the deformation in the contact area, which is justified from the point of view of the accuracy of calculations, since otherwise the impact force magnitude will be overestimated. When modeling the load impact interaction and the considered rod system, it is assumed that the falling load has the shape of a cylinder with a certain generatrix length. Linearization of the relationship between the force and deformation of cylindrical surfaces is used. The proposed technique for modeling the amplitude of transverse oscillations makes it possible to further study the oscillatory process characteristics depending on the falling load mass and its pre-impact velocity, as well as on the rod system configuration. The relevance of the work for the calculation of structural elements of various purposes that are subject to impact is emphasized, since the presented model can be used for engineering calculations of a wide class of bar systems. [ABSTRACT FROM AUTHOR]

The formation feasibility for a neural network based on crossbar-array architecture on a silicon substrate has been demonstrated. The possibility of neural network implementation in the form of crossbar-array architecture on a silicon substrate has been shown. It is suggested that the crossbar-array architecture (a set of orthogonal nanometer conductors with a titanium oxide layer in between, the conductivity of which is sensitive to applied voltage) be configured using local anodic oxidation. Test results for process parameters used in local anodic oxidation of silicon and titanium to create elements of a memristor-based neural matrix are presented. [ABSTRACT FROM AUTHOR]

Memristive neural networks (MNNs) attract the attention of many researchers because memristor can mimic the learning mechanism of biologic neuron, spike timing-dependent plasticity (STDP). While STDP brings huge potentials on many applications for memristive neural networks, it also gives complex calculation process for hardware implement. In this work, a non-STDP learning mechanism is proposed, which is implemented in two common frameworks including feedforward neural network and crossbar. The non-STDP learning mechanism relies on the linear relationship between the value of memristor and area of input spikes, which gives the proposed method a simple calculation process and better hardware compatibility. Experimental results show that the non-STDP learning mechanism can help to achieve good hardware performance in both feedforward neural network and crossbar frameworks. Compared with STDP based memristive neural networks, the proposed method can save 2.19%-24.4% hardware resource (ALMs) and improve 1.56-12.25 MHz processing speed under a set of different network scales. In future, some other complex memristor models with non-STDP learning mechanism should be taken into consideration, which will give more room for practical applications of memristive neural networks. [ABSTRACT FROM AUTHOR]

The property of the natural parallelization of matrix-vector operations inherent in memristor crossbars creates opportunities for their effective use in neural network computing. Analog calculations are faster by orders of magnitude than calculations on a central processor and on graphics accelerators. Furthermore, the energy costs of mathematical operations are significantly lower. At the same time, the low level of accuracy is characteristic of analog computing. In relation to this, studying the dependence of the neural network's quality on the accuracy of setting its weights is relevant. The paper considers two convolutional neural networks trained on the MNIST (handwritten digits) and CIFAR_10 (airplanes, boats, cars, etc.) data sets. The first convolutional neural network consists of two convolutional layers, one subsample layer and two fully connected layers. The second one consists of four convolutional layers, two subsample layers and two fully connected layers. Calculations in convolutional and fully connected layers are performed through matrix-vector operations that are implemented on memristor crossbars. Subsampling layers imply the operation of finding the maximum value from several values. This operation can be implemented at the analog level. The process of training a neural network runs separately from data analysis. As a rule, gradient optimization methods are used at the training stage. It is advisable to perform calculations using these methods on a CPU. When setting the weights, 3–4 precision bits are required to obtain an acceptable recognition quality in the case the network is trained on MNIST, and 6–8 precision bits are required if the network is trained on CIFAR_10. [ABSTRACT FROM AUTHOR]

In multi-processor system-on-chips, on-chip interconnection plays a significant role. The type of on-chip architecture being used in an application decides the performance of that application. Hence, a quick and versatile network-on-Chip (NoC) simulator, particularly for the larger designs, is essential to explore and find the best suitable NoC configuration for individual applications. An FPGA-based NoC simulation framework has been proposed in this work. The crossbar switch of the NoC router with buffers and five ports has been embedded in the wide multiplexers of the DSP48E1 slices. The distinctive feature of dynamic mode functionality of the DSP48E1 slices every clock cycle depending on the control signals of multiplexer plays a crucial role in incorporating the crossbar functionality. A substantial decrease in the configurable logic blocks (CLBs) utilization of NoC topologies on the FPGA has been observed by embedding the functionality of the crossbar on the DSP48E1 slices. Since there is a reduction in the use of CLB resources employing the crossbar based on DSP48E1, topologies of larger sizes can be simulated. 6 × 6 Mesh topology with the DSP crossbar implementation consumes 36% fewer lookup tables (LUTs) and 40% fewer flip flops than the Mesh topology with CLB-based crossbar implementation. 41% fewer LUTs and 23% fewer slices are consumed by the proposed work with respect to the state-of-the-art CONNECT NoC generation tool. Compared to DART, a reduction of 86% and 80% in LUTs and slices has been observed with respect to the proposed work. Hoplite-DSP implements the unidirectional Torus topology with no buffers considering the deflective routing algorithm. The proposed work targets Mesh-based topologies with buffers and bidirectional ports with XY and look-ahead routing algorithms. [ABSTRACT FROM AUTHOR]

Memristor crossbars are capable of implementing learning algorithms in a much more energy and area efficient manner compared to traditional systems. However, the programmable nature of memristor crossbars must first be explored on a smaller scale to see which memristor device structures are most suitable for applications in reconfigurable computing. In this paper, we demonstrate the programmability of memristor devices with filamentary switching based on LiNbO3, a new resistive switching oxide. We show that a range of resistance values can be set within these memristor devices using a pulse train for programming. We also show that a neuromorphic crossbar containing eight memristors was capable of correctly implementing an OR function. This work demonstrates that lithium niobate memristors are strong candidates for use in neuromorphic computing. [ABSTRACT FROM AUTHOR]

In this paper, resistive random access memory (RRAM)-based crossbar arrays with the cell structure of Pt/[AlO/HfO]/TiN were fabricated by using atomic layer deposition (ALD) technique. The RRAM devices in the arrays show excellent performances such as good uniformity and high reliability. Based on the fabricated RRAM array, a complete set of basic logic operations including NOR and XNOR were successfully demonstrated. [ABSTRACT FROM AUTHOR]

Nanotechnology-based manufacturing, relying on self-assembly of nanotubes or nanowires, has shown promising potentials for future nanoscale circuit designs. However, high defect density and extreme process variations for crossbar-based nanoarchitectures are expected to be fundamental design challenges. Consequently, defect and variation issues must be considered in logic mapping on nanoscale crossbars. In this paper, we establish a mathematical model for the simultaneous variation and defect-aware logic mapping of multi-outputs crossbar arrays. We model this problem using a new sub-weighted-graph isomorphism problem and propose a greedy algorithm for the variation- and defect-aware logic mapping. Based on Monte-Carlo simulation, we compare the proposed technique with other logic mapping techniques such as, variation-unaware and exhaustive search mapping in terms of accuracy as well as runtime. Results show that the effectiveness of our new mapping technique in variation and defect tolerance as well as run time improvement. [ABSTRACT FROM AUTHOR]

In this article, we comprehensively review recent progress in the ReRAM cell technology for 3D integration focusing on a material/device level. First we briefly mention pioneering work on high-density crossbar ReRAM arrays which paved the way to 3D integration. We discuss the two main proposed 3D integration schemes-3D horizontally stacked ReRAM vs 3D Vertical ReRAM and their respective advantages and disadvantages. We follow with the detailed memory cell design on important work in both areas, utilizing either filamentary or interface-limited switching mechanisms. We also discuss our own contributions on HfO-based filamentary 3D Vertical ReRAM as well as TaO/TiO bilayer-based self-rectifying 3D Vertical ReRAM. Finally, we summarize the present status and provide an outlook for the nearterm future. [ABSTRACT FROM AUTHOR]

The problems of programming memristor array (crossbar) are considered. A voltage pulse duration to set the desired value of memristor resistance is evaluated. An algorithm for mapping weight matrix of the neurons layer onto memristor crossbar is proposed. A simulation of adaptive adder with memristor synapses is carried out in the LTspice using the proposed method of mapping. The possibility of using the adaptive adder for image recognition is demonstrated. [ABSTRACT FROM AUTHOR]

On-chip interconnection has posed significant challenges in multiprocessor system on chip (MPSoC) design paradigm, especially in big data era. With respect to the state-of-the-art, crossbar-based interconnection methodologies are still efficient for FPGA-based small-scale heterogeneous MPSoCs. This paper proposes a crossbar-based on-chip interconnection scheme, named CRAIS. CRAIS utilizes reconfigurable crossbar interconnections between microprocessors and intellectual property (IP) cores in MPSoC. The hardware interconnection can be dynamically reconfigured during execution. Empirical results on FPGA prototype demonstrate that CRAIS can achieve more than 7X speedup compared with the state-of-the-art StarNet approach, while it only utilizes 21%∼35% hardware resources of StarNet. [ABSTRACT FROM AUTHOR]

This paper presents and evaluates router architectures for security networks. Through extensive simulations, the DAMQWR and PD-CB router architecture is shown to best support true fully adaptive routing capability of deadlock recovery schemes while maximizing network performance (102 % higher throughput and 86 % lower network latency than other architectures). Therefore, this router architecture can build a more stable security network by providing a higher network performance. [ABSTRACT FROM AUTHOR]

In this paper, a neuromorphic crossbar circuit with binary memristors is proposed for speech recognition. The binary memristors which are based on filamentary-switching mechanism can be found more popularly and are easy to be fabricated than analog memristors that are rare in materials and need a more complicated fabrication process. Thus, we develop a neuromorphic crossbar circuit using filamentary-switching binary memristors not using interface-switching analog memristors. The proposed binary memristor crossbar can recognize five vowels with 4-bit 64 input channels. The proposed crossbar is tested by 2,500 speech samples and verified to be able to recognize 89.2% of the tested samples. From the statistical simulation, the recognition rate of the binary memristor crossbar is estimated to be degraded very little from 89.2% to 80%, though the percentage variation in memristance is increased very much from 0% to 15%. In contrast, the analog memristor crossbar loses its recognition rate significantly from 96% to 9% for the same percentage variation in memristance. [ABSTRACT FROM AUTHOR]

This work explores anti-serial (anti-parallel) memristive switches-ASMs (APMs)-as potential cross-point elements in nano-crossbar resistive random access memory arrays. The memory operation principles for both device combinations are shown in detail. The effectiveness of these memristive structures to the solution of the parasitic conducting (current sneak paths) problem is presented via an analytical approach which is based on the basic setup of resistive crossbar memories. Simulation results of crossbars of up to 4,096 elements, arranged in quadratic configurations, are conducted. The provided results supplement this comprehensive analysis of APMs and ASMs, outlining their overall performance characteristics and commenting on their applicability to the practical realization of large crossbar memory systems. Finally, a special array topology is applied to an ASM-based crossbar memory. Its performance is compared to the performance of the pure ASM-based memory. The conducted simulations reveal significantly improved read-out voltage margins which further contribute to addressing the parasitic current paths which prevent the reliable operation of memristive crossbar circuit topologies. [ABSTRACT FROM AUTHOR]

This paper deals with an in-line network security processor (NSP) design that implements the Internet Protocol Security (IPSec) protocol processing for the 10 Gbps Ethernet. The 10 Gbps high speed data transfer, the IPSec processing including the crypto-operation, the database query, and IPSec header processing are integrated in the design. The in-line NSP is implemented using 65 nm CMOS technology and the layout area is 2.5 mm×3 mm with 360 million gates. A configurable crossbar data transfer skeleton implementing an iSLIP scheduling algorithm is proposed, which enables simultaneous data transfer between the heterogeneous multiple cores. There are, in addition, a high speed input/output data buffering mechanism and design of high performance hardware structures for modules, wherein the transfer efficiency and the resource utilization are maximized and the IPSec protocol processing achieves 10 Gbps line speed. A high speed and low power hardware look-up method is proposed, which effectively reduces the area and power dissipation. The post simulation results demonstrate that the design gives a peak throughput for the Authentication Header (AH) transport mode of 10.06 Gbps with the average test packet length of 512 bytes under the clock rate of 250 MHz, and power dissipation less than 1 W is obtained. An FPGA prototype is constructed to verify the function of the design. A test bench is being set up for performance and function verification. [ABSTRACT FROM AUTHOR]

As far as ultra-dense crossbars are related to correspondingly dense wire arrays, the crossbar route to tera-scale integration depends on the availability of preparation techniques for wire arrays with density of 10 cm or more. This linear density implies, for a planar arrangement, a pitch of 10 nm or less, which not only is at the limits of the current technical possibilities, but also can modify appreciably the band structure of silicon. A dramatic increase of density could only be achieved if it were possible to organize the nanowires in a three-dimensional fashion still exploiting the planar technology. In this work processes are described for the fabrication of out-of-plane, vertically arranged, polycrystalline silicon nanowires via a rigorously top-down batch process. These techniques are consistent with the production of wire arrays with linear density (projected on the surface) larger than that achievable with any other proposed top-down process. Used for the fabrication of the bottom wire arrays of crossbars, these processes should eventually allow a cross-point amount per unit area in excess of 10 cm, thus providing candidate technologies for ultra tera scale integration. The technique developed for such out-of-plane crossbars can be used to implement new functions like coils, solenoids and transformers. [ABSTRACT FROM AUTHOR]

Recently announcement of a physical realization of a fundamental circuit element called memristor by researchers at Hewlett Packard (HP) has attracted so much interest worldwide. Combination of this newly found element with crossbar interconnect technology, opened a new field in designing configurable or programmable electronic systems which can have applications in signal processing and artificial intelligence. In this paper, based on the simple memristor crossbar structure, we will propose a new mixed analog-digital circuit as a hardware implementation of the sign-sign least mean square (LMS) adaptive filter algorithm. In this proposed hardware, any multiplication and addition is performed with infinite precision and there is no necessity for the quantization of the input signal. Since the coefficients of the filter are stored in the switches of the crossbar, they can remain unchanged theoretically for an infinite period of time. [ABSTRACT FROM AUTHOR]

Godson-3 is the latest generation of Godson microprocessor family. It takes a scalable multi-core architecture with hardware support for accelerating applications including X86 emulation and signal processing. This paper introduces the system architecture of Godson-3 from various aspects including system scalability, organization of memory hierarchy, network-on-chip, inter-chip connection and I/O subsystem. [ABSTRACT FROM AUTHOR]

The effect of the mode order of a vertical cavity surface emitting laser on the surface normal coupling efficiency into a horizontal optical waveguide is discussed. The numerical results are compared with experimental observations. [ABSTRACT FROM AUTHOR]