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In this study, a three-level static RAM cell with a single BL based on 16 nm BWG CNFET technology is proposed for use in high-performance IoT platforms. The proposed memory structure in a bit-interleaved architecture compatible design consists of a standard triple buffer gate (STB) based on the BWG CN-TGDI method and a pair of transmission gates as an access network. In the STB cell structure, the threshold voltage calibration by the flat band voltage parameter of the CNTs has been used to improve the static noise margin at logic level '1'. In addition, pseudo-resistor and stacked transistor structures have been used to control the single static current path during logic level '1' generation and cell leakage current, respectively. The simulation results based on the Monte Carlo method show that the hardware performance parameters PDP and EDP for the proposed design have been improved by 38.8% and 31%, respectively, compared to the counterpart structure. Moreover, the proposed architecture has shown a more reasonable result in terms of noise immunity than the best-performing design by 1.93 times. Finally, to investigate a real-world application, the triple memory structure has been used to store the colored QR code image with the data content of three values using the proposed hardware algorithm. The obtained results for the quality evaluation metrics, PSNR and MSSIM, emphasize the suitability of the proposed memory architecture for the development of next-generation SoCs. [ABSTRACT FROM AUTHOR]

The article presents two multipliers equipped with error compensation techniques, utilizing approximate 4:2 compressors to minimize energy consumption. Compared to previous approximate multipliers with error compensation circuit, the proposed designs named, "M00" and "M01", strike a good balance between accuracy and energy consumption. Although the reduction in the number of transistors has significantly decreased the energy consumption of M00, the accuracy of this design is still more than adequate for real-world applications such as image processing and neural networks. On the other hand, M01 attains high precision while consuming less energy than other multipliers. This article compares the proposed designs with existing multipliers using HSPICE tool in 7 nm FinFET technology. Moreover, the accuracy and quality of the proposed multipliers are evaluated using MATLAB. The results reveal that both proposed designs are very efficient in image processing. According to the results, M00 has the lowest energy consumption among the considered designs. M00 is about 7% better than its counterpart in terms of the power-delay-product parameter (5% Pdynamic and 48% Pstatic). M01 presents favorable results in the sharpening, smoothing, and Discrete Cosine Transform processes. [ABSTRACT FROM AUTHOR]

A new 1-bit digital comparator named 14T-SR-GDI is presented with gate-diffusion-input (GDI) and single-swing-restoration (SR) techniques to attain internal gates with high driving capability. The comparator has 14 transistors which produce full-swing outputs with low power consumption. In the 14T-SR-GDI, boosted inner signals are used to activate the output gates which result in a high-speed circuit with effective scalability and the enhanced driving capability for multi-bit structures. The comparator has a low power delay product (PDP) due to the small numbers of internal nodes and capacitances and efficient power-ground-free gates. The 14T-SR-GDI comparator, fully SR-GDI-based AND, and OR gates, construct a new tree structure for multi-bit magnitude comparators including 2-bit, 4-bit, 8-bit, and 16-bit comparators. The proposed 1-bit comparator is used in image processing for difference detection, and its efficiency is proved by image quality parameters. The post-layout simulations are performed for the 1-bit to 16-bit structures under TSMC 90 nm technology. The extracted results express a PDP with an average difference of 9.59% between the regular and post-layout modes. Also, the proposed 16-bit comparator is embedded in a pad with a total area of 4331.25 μm2. The designed magnitude comparators are key components in digital signal processors (DSPs). [ABSTRACT FROM AUTHOR]

Gate diffusion input (GDI) method using a simple cell makes it possible to design low-power logic gates with reduced chip area and less complexity. In this work, a novel design of single-bit optimized reversible logic-based magnitude arithmetic unit (RMAU) circuit, using appropriate standard reversible gates with carbon nanotube (CNT) field-effect transistors (CNTFETs), based on modified-GDI (m-GDI) method for nanoscales is presented. In order to optimize the performance of the proposed circuit, and to achieve minimum power consumption and propagation delay, transistor sizes are adjusted using the non-dominated sorting genetic algorithm II (NSGA-II) in MATLAB tool. The simulation results show improvement in evaluating the figure of merits in worst-case delay and power consumption of the proposed optimized arithmetic unit, in comparison with a non-optimized RMAU circuit using a similar design method but counterpart structures. The effects of different process parameters (such as the diameter of CNTs) and voltage and temperature (PVT) variations are extensively evaluated by the Monte Carlo procedure in standard 32 nm technology utilizing the Synopsys HSPICE simulator. According to the outcomes obtained, the proposed optimized RMAU circuit is robust against PVT variations and noise-tolerable criterions, compared to those competitors with similar design in non-optimized conditions. The proposed optimized and non-optimized circuits were used in image processing as real environment assessments, and results depicted their excellent ability in being implemented in various large reversible-based applications, such as future generations of FPGA chips and CNTFET-based computers. [ABSTRACT FROM AUTHOR]

The power requirements of wireless sensor networks and internet of things (IoT) applications heavily rely on batteries. It is crucial that the memory cells utilized in these applications must consume low-power to prolong the battery life. In this paper, a static-random access memory (SRAM) cell is introduced that incorporates eleven carbon nanotube field-effect transistors (CNTFETs). The proposed 11T CNTFET SRAM cell employs a single-ended approach for reading and writing data and read-decoupled approach to access data in the bit cell. In addition to this, Schmitt-trigger (ST) inverter is incorporated within the bit cell, to enhance its stability and power efficiency. To evaluate the performance of the proposed 11T CNTFET SRAM cell, 32 nm CNTFET model developed by the Stanford University- and HSPICE simulation tool are used for the simulations. The proposed 11T CNTFET bit cell’s results show write power, hold power, read power, write static noise margin, hold static noise margin read static noise margin, write delay and read delay of 0.182 nW, 0.2 nW, 0.197 nW, 453.5 mV, 380.5 mV, 383.3 mV, 102 pS and 41.9 pS, respectively at VDD = 0.9 V. Comprehensive parametric simulations are also carried out to analyze the impact of various CNTFET parameters on performance metrics of proposed SRAM cell. The performance of proposed SRAM is fairly compared with existing SRAM cells implemented with CNTFETs and results are found to be quite encouraging. The proposed SRAM cell finds its suitability for use in designing memory devices targeted for wireless sensor networks, Internet of Things and smart biomedical gadgets. [ABSTRACT FROM AUTHOR]