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In the digital age, medical images have become an indispensable tool for the diagnosis of certain diseases and health prevention. In the face of increasing computing power and diverse means of attack, as well as the need for real-time processing of medical images, traditional encryption and watermarking techniques may no longer be sufficient to effectively protect the integrity and copyright of these sensitive images. Based on this practical requirement, this study proposes a novel digital watermarking algorithm for copyright authentication of ophthalmic medical images using a chaotic system. This algorithm integrates a novel three-dimensional pupal equilibrium curved hyperchaotic system (PCHCS) to enhance the encryption effect of the AES algorithm. Clever embedding of watermarks in the edge regions of the ROI using Least Significant Bit (LSB) technology ensures minimal impact on diagnostic quality. RONI uses DCT transform for processing to enhance copyright authentication. The chaotic system and watermarking algorithm have been implemented on FPGA to further demonstrate their feasibility. The PSNR of the proposed system can reach more than 55 dB and the SSIM value is close to 1. The values of NC and BER also perform well under various attacks. Experimental results show that the designed watermarking algorithm has good invisibility and robustness. [ABSTRACT FROM AUTHOR]

Currently, design and application of discrete memristor aroused much interests. In this paper, digital integrated circuits of discrete memristive systems are designed based on the proposed fixed-point specific processor with acceleration instructions. The discrete memristor and the discrete memristive chaotic map are designed based on the trigonometric function including the Sine function and the Cosh function. It shows that the chaotic system has rich dynamics and can generate hyperchaos. To design a universal digital integrated circuit implementation method, a fixed-point specific processor is designed which is programmable. As a result, the chip layout of the memristive systems is obtained. Numerical simulations are completed in accordance with the Matlab simuation results. Compared with the ASIC(Application-Specific Integrated Circuit) based method, the digital circuit in this paper is two times larger in area and has 50% more power consumption due to the trigonometric and hyperbolic functions, but it can be reprogrammed to implement different models. It provides a new technical scheme for the application of discrete memristors in different engineering application fields. [ABSTRACT FROM AUTHOR]

Basic analog–digital motion detection circuits with low power consumption were proposed based on the vertebrate retina. The motion sensor based on the retina is constructed with a one- or two-dimensional array of the unit circuits. The proposed unit circuit for motion detection is constructed with an analog circuit for photoelectric conversion and the digital circuit for generating the motion signal. The metal oxide semiconductor (MOS) transistors utilized to the analog circuits are operated in the subthreshold region. The analog circuit has the characteristic of the low power consumption. The proposed circuit was evaluated by the simulation program with integrated circuit emphasis (SPICE) with the 0.6 μm complementary metal oxide semiconductor (CMOS) process. The test circuits of basic digital circuits were fabricated with the same process. In the simulation and the experiment, the power supply voltage was set to the low voltage. We found that the digital circuit becomes low power consumption because the MOS transistors was operated in the subthreshold region by setting the low voltage. The proposed circuit is characterized by the simple structure and the low power consumption. In the future, the novel motion detection sensor with low power consumption can be realized by applying the integrated circuits constructed with the array of the proposed unit circuits. [ABSTRACT FROM AUTHOR]

Novel basic analog–digital edge detection circuits in this research were proposed based on the vertebrate retina. The vertebrate retina is a pre-processor for image processing in the brain and has superior functions such as edge detection and motion detection. The proposed circuit was evaluated by the simulation program with integrated circuit emphasis (SPICE) with the 0.6 μm complementary metal oxide semiconductor (CMOS) process. The simulation results with SPICE showed that the proposed circuits can operate normally. The test integrated circuit of the unit circuit was fabricated with a 0.6 μm CMOS process. The measured results showed that the unit circuit can detect the edge position. The test integrated circuits of one-dimensional array of unit circuits were fabricated with the same process. The measured results showed that the one-dimensional circuits can detect the edge position. In the future, the realization of a new vision sensor can be expected using the proposed circuit. [ABSTRACT FROM AUTHOR]

In this work, a digital circuit for fast scan voltammetry (FSV) was developed based on dual-frequency method. It consists of six main modules including the microcontroller unit, signal generator module, solution resistance measurement module, ohmic drop automatic compensation module, keying module and display module. By online measuring the solution resistance without any interference from capacitive impedance first, the ohmic drop compensation could be precisely carried out, bringing reliable FSV detection. RC dummy cell, dummy cell with pseudo-Faradaic impedance and actual electrochemical cell were used to verify the performance of automatic ohmic drop compensation. Results show that, FSV could be performed using a conventional electrode with the scan rate up to 2400 V/s. And, a handheld device was manufactured with a weight of 100 g and a size of 9 × 6 × 3 cm, costing only $35. It provides a simple, reliable and stable FSV plateau for electrochemical detection. [ABSTRACT FROM AUTHOR]

In the present research article, we have proposed an analytical compact model for nanowire Junctionless Gate-All-Around (JLNGAA) MOSFET validated in all transistor's operation regimes. The developed model having an analytical compact form of the current expressions, based on surface potential (ΦS), obtained from approximated solutions of Poisson's equation. The proposed model has implemented in standard Verilog-A language using SMASH circuit simulator in order to be used in various commercial circuit simulators. The proposed model has also validated using ATLAS-TCAD simulation for various physical parameters such as the channel doping concentration (Nd) and the channel radius (R) of JLNGAA MOSFET. Finally, based on the developed Verilog-A JLNGAA MOSFET model, we have tested it in four types of low voltage circuits, CMOS inverter, CMOS NOR-Gate, an amplifier and a Colpitts oscillator. [ABSTRACT FROM AUTHOR]

In this paper, a two-wing chaotic system is transformed into a four-wing chaotic system and an eight-wing chaotic system using fractal processing and the dynamic characteristics of new multi-wing chaotic systems are analyzed. The encryption of the image is accomplished by combining the eight-wing chaotic system and the improved AES algorithm. The number of AES encryption rounds is reduced to make it more suitable for image encryption. To further improve the encryption efficiency, the chaotic system circuit and AES parallel computation are designed and implemented on FPGA. Finally, the high performance of the chaotic system is demonstrated by the satisfactory encryption effect. This methodology provides a promising direction for the study of real-time image encryption. [ABSTRACT FROM AUTHOR]

In this paper, a new fundamental cell in positive feedback source coupled logic is presented, which is an improvement over the existing fundamental cell employed in digital circuit design in various high resolution mixed-signal integrated circuits. The operation of the existing fundamental cell relies on using large sized transistor in its centre branch, resulting in significantly larger implementation area. The proposed fundamental cell incorporates multi-threshold transistor in the center branch thereby allowing designer to use reduce its dimension and hence the area. The impact of the proposed modification is examined by configuring the cell as two input exclusive OR (XOR2) gate. The behaviour is analysed in terms of static and propagation delay parameters which are modelled and a design procedure is also elaborated. The theoretical prepositions are verified by designing and simulating for various operating conditions using model parameters of 180 nm CMOS technology node. A maximum error of 27% is observed between the simulated and predicted parameters. The process variation study through Monte Carlo analysis and PVT variations identifies the proposed fundamental cell based circuit as less prone to variations in comparison to existing fundamental cell based counterparts. A full adder, as an application of the proposed fundamental cell, shows a significant (66%) area reduction while delay, power and PDP are within 4% of their corresponding values for the existing one. [ABSTRACT FROM AUTHOR]

It is proposed to use transistor-transistor logic (TTL) for future fast, low-power digital electronic circuits. A relaxation quantum transistor can be the basic element of these circuits. This approach allows us to circumvent the difficulties of using field effect transistors based on nanowires. [ABSTRACT FROM AUTHOR]

This paper extends the concept of Karnaugh map from a logical function to a logical system, thereby allowing both the state transition graph and state transition matrix of a logical system, as well as a digital circuit, to be constructed directly. It is found that the Karnaugh map of a logical system is actually a two-dimensional state transition table or, equivalently, a table-like state transition graph and is also a grid-type state transition matrix. For constructing the state transition graph and state transition matrix of a logical system, the computational complexities of the methods based on the proposed Karnaugh map are exponentially lower than those of the existing methods. The Karnaugh maps of logical systems are then used in the analysis and design of clocked sequential circuits and in the simplification of multioutput gate circuits. Some illustrative examples and simulations are presented to demonstrate the results and their applications. [ABSTRACT FROM AUTHOR]

An adaptive voltage scaling (AVS) DC-DC converter based on embedded pulse skip modulation (PSM) is presented in this paper. As AVS technique developing, the supply voltage of digital circuits can be scaled adaptively with the changing of operation frequency and working environment. The critical path replica (CPR) is widely used in AVS implementation. The worst-case margin is relaxed by probing and tracking the CPR delay time of target applications. Consequently, the energy consumption of digital circuits is decreased significantly with supply voltage reduced. At the same time, in order to improve the efficiency of DC-DC converter especially in light load, the PSM mode has been used in proposed circuit structure. The circuit of AVS DC-DC converter based on embedded PSM has been implemented and fabricated in a standard 0.13 μm CMOS process which occupies 1.2 mm active silicon areas. The experimental results show that, the output voltage of the DC-DC converter is well regulated from 0.6 to 1.5 V when the clock frequency varies within the range of 30-150 MHz. The maximum energy saving of 83 % is obtained with the proposed circuit structure compared to the traditional fixed voltage. [ABSTRACT FROM AUTHOR]

We proposed in this study the simple system for detecting the sound localization based on the biological auditory system. The proposed system is constructed with the simple complementary metal oxide semiconductor (CMOS) analog-digital circuit based on the biological auditory system and two microphones. The proposed circuit consists of the delay lines and the comparators. The structure of the proposed circuit is simple. The test circuit and system were developed. The test circuit was fabricated with discrete metal oxide semiconductor (MOS) transistors on the breadboard. The experimental results of the test system showed that the proposed circuit can generate the output signal for detecting the position of the sound of the target. We can realize a new target tracking system by applying the proposed system in this research. [ABSTRACT FROM AUTHOR]

Simple analog-digital circuits for detecting the motion direction based on the information processing of the vertebrate retina were proposed. A network constructed with an array of proposed circuits was applied to a mobile robot. A test circuit was fabricated using discrete metal oxide semiconductor (MOS) transistors on a breadboard. The measured results of the test circuit showed that the unit circuit can output a motion signal. The motion sensor for detecting the movement direction, which consists of an array of unit circuits, was connected to the microcomputer introduced in the mobile robot. It was clarified that the proposed circuits can control the mobile robot. [ABSTRACT FROM AUTHOR]

Image processing represents a research field in which high-quality solutions have been obtained using various soft computing techniques. Evolutionary algorithms constitute a class of stochastic search methods that are applicable in both optimization and design tasks. In the area of circuit design Cartesian Genetic Programming has often been utilized in combination with an algorithm of Evolutionary Strategy. Digital image filters represent a specific class of circuits whose design can be performed by means of this approach. Switching filters are advanced non-linear filtering techniques in which the main idea is to detect and filter the noise pixels while keeping the uncorrupted pixels unchanged in order to increase the quality of the resulting image. The aim of this article is to present a robust design technique based on Cartesian Genetic Programming for the automatic synthesis of switching image filters intended for real-time processing applications. The robustness of the proposed evolutionary approach is evaluated using four design problems including the removal of salt and pepper noise, random shot noise, impulse burst noise and impulse burst noise combined with random shot noise. An extensive evaluation is performed in order to compare the properties of the evolved switching filters with the best conventional solutions. The evaluation has shown that the evolved switching filters exhibit a very good trade off between the quality of filtering and the implementation cost in field programmable gate arrays. [ABSTRACT FROM AUTHOR]

In this article, we introduce a new design for DNA logic gates based on enzymatic restriction of DNA strands. We present a construction for a set of one and two-input logic gates and argue that our construction can be generalized to implement any Boolean operation. A key feature of our design is its time-responsiveness, in the presence of appropriate fuels our circuit can operate continuously and generate a time-dependent output in response to a time-dependent input. Moreover, modulo connectivity information, the strand design and circuit design phases are decoupled. [ABSTRACT FROM AUTHOR]

We propose an analog-digital circuit for detecting the movement of an object. The proposed unit circuit is a simple structure since the digital part of the circuit is constructed with only one NOT circuit and one NOR circuit. The measured results on a constructed test circuit showed that the proposed circuit can output the pulsed voltage (motion signal) when an object moves on the circuit. We proposed and constructed the system in this study in order to track target. Since the array in the proposed circuits was introduced at the first stage of the system, the circuit for tracking the target became a simple structure. It was clear from the measured results of the test system that it can track and capture a target in the center of the input section. [ABSTRACT FROM AUTHOR]

In this study, we propose an analog-digital circuit for sound localization based on the biological auditory system. The proposed circuit is constructed with a delay line and a comparator. The delay line was constructed with the simple analog circuits of the current mode. The NOR circuit was used as the comparator. The current mode delay line was evaluated by a simulation program with integrated circuit emphasis (SPICE). The test circuit was fabricated by discrete metal oxide semiconductor (MOS) transistors on the breadboard. The result with SPICE and the measured results of the test circuit showed that the time for transmitting a signal on the current mode delay line becomes shorter when the sound of the target is greater. When the sound of the target was small, the time taken to transmit the signal became longer. The proposed circuit for sound localization was evaluated by SPICE. The result with SPICE showed that the circuit can generate a signal to detect the position of the sound of the target. We can realize a new target-tracking system by applying this novel circuit based on the biological auditory system to a previously proposed tracking system based on the biological vision system. [ABSTRACT FROM AUTHOR]

In this paper, a new design of adiabatic circuit, called the quasi-static efficient charge recovery logic (QSECRL) is proposed. To achieve minimum energy consumption, this paper proposes a technique to reduce channel resistance and remove diodes from the signal path. This design method can be implemented in both combination logic and sequential logic. The counter circuit and the 8-bit carry look-ahead (CLA) circuit, a more complex circuit, are selected to evaluate this proposed design. All simulations in this paper have been implemented by SPICE with the 0.8 μm MOSIS technology MOS transistor model under 2-volt (peak-peak) sinusoidal power-clock supply. The results show significantly improved performance of the 8-bit CLA circuit with 20–30 fJ and 70 fJ energy consumption at 10–100 MHz and 500 MHz operating frequency, respectively. [ABSTRACT FROM AUTHOR]

Copyright of Annals of Telecommunications is the property of Springer Nature and its content may not be copied or emailed to multiple sites or posted to a listserv without the copyright holder's express written permission. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.)

Copyright of Annals of Telecommunications is the property of Springer Nature and its content may not be copied or emailed to multiple sites or posted to a listserv without the copyright holder's express written permission. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.)

This paper proposes two bounded arithmetic operations, which are easily realized with current signals. Based on these two operations, a bounded algebra system suitable for describing current-mode digital circuits is developed and its relationship with the Boolean algebra, which is suitable for representing voltagemode digital circuits, is investigated. Design procedure for current-mode circuits using the proposed algebra system is demonstrated on a number of common circuit elements which are used to realizd arithmetic operations, such as adders and multipliers. [ABSTRACT FROM AUTHOR]

Copyright of Annals of Telecommunications is the property of Springer Nature and its content may not be copied or emailed to multiple sites or posted to a listserv without the copyright holder's express written permission. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.)

Copyright of Annals of Telecommunications is the property of Springer Nature and its content may not be copied or emailed to multiple sites or posted to a listserv without the copyright holder's express written permission. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.)

Copyright of Annals of Telecommunications is the property of Springer Nature and its content may not be copied or emailed to multiple sites or posted to a listserv without the copyright holder's express written permission. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.)

Le synchronisateur primaire sert dans une chaîne de transmission de données par satellite à restituer le rythme numérique et à décider des symboles contenus dans le message mic transmis. L'étude théorique et expérimentale d'un synchronisateur primaire entièrement numérique réalisé avec des circuits logiques standard est présentée. Ce synchronisateur fournit à partir du signal mic échantillonné une raie discrète de fréquence double du rythme numérique. Cette raie est isolée par une boucle d'asservissement de phase numérique qui commande un filtre adapté numérique. Les résultats théoriques et expérimentaux montrent un temps moyen d'acquisition très court, de l'ordre de 4 à 5 symboles, et une dégradation inférieure à 2 dB pour un domaine E/N compris entre + 2 dB et + 12 dB. Bit synchronizers are used in satellite data communications systems to restore the data rate. They provide means to data detection. The paper concerns the theoretical analysis supported by the simulation and the pratical measurements of a digital self bit synchronizer implemented with standart ttl logic. This self bit synchronizer is composed of a non linear element which delivers from the sampled and quantized pcm signal a spectral line at frequency twice the data rate. This spectral line is filtered by a digital phase locked loop and is used to drive a digital matched filter data detector. Theoretical and experimental results show a very small mean acquisition time (about 4 or 5 bit duration) and a degradation lower than 2 dB for snr ranging from + 2 dB to + 12 dB. [ABSTRACT FROM AUTHOR]

A practical method of directly designing sequential circuits by use of state transition diagrams is described. This method has many advantages. It is easy to use and especially suitable for multi-input and multi-state conditions. [ABSTRACT FROM AUTHOR]