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Fog computing is considered a formidable next-generation complement to cloud computing. Nowadays, in light of the dramatic rise in the number of IoT devices, several problems have been raised in cloud architectures. By introducing fog computing as a mediate layer between the user devices and the cloud, one can extend cloud computing's processing and storage capability. Offloading can be utilized as a mechanism that transfers computations, data, and energy consumption from the resource-limited user devices to resource-rich fog/cloud layers to achieve an optimal experience in the quality of applications and improve the system performance. This paper provides a systematic and comprehensive study to evaluate fog offloading mechanisms' current and recent works. Each selected paper's pros and cons are explored and analyzed to state and address the present potentialities and issues of offloading mechanisms in a fog environment efficiently. We classify offloading mechanisms in a fog system into four groups, including computation-based, energy-based, storage-based, and hybrid approaches. Furthermore, this paper explores offloading metrics, applied algorithms, and evaluation methods related to the chosen offloading mechanisms in fog systems. Additionally, the open challenges and future trends derived from the reviewed studies are discussed. [ABSTRACT FROM AUTHOR]

Nanomagnetic logic (NML) is a promising candidate for the real implementation of quantum-dot cellular automata circuits and can be a proper alternative or complement to CMOS circuits. Like any other nanoscale technologies, NML circuits are also subject to fabrication variations. These variations along with fluctuations caused by thermal noise can affect the performance of these circuits. Therefore, design of NML circuits with high testability is an absolute necessity. Circuits based on conservative logic are inherently testable because of their specific properties. In this paper, considering the physical and geometrical properties of nanomagnets, a nanomagnetic conservative quantum-dot cellular automata gate is designed and evaluated. This circuit can be used as the basic block for the realization of more complex conservative NML circuits. To implement this circuit, the design of the clocked nanomagnetic majority gate is also provided. The OOMMF physical simulation tool is used for simulation and evaluation. The results show the correct functionality of the proposed conservative gate at room temperature. It operates about 34% faster than the NML Fredkin gate. Moreover, the NML version of the conventional Fredkin gate takes 90% more area than the proposed design. [ABSTRACT FROM AUTHOR]

Quantum-dot cellular automata (QCA) is a computational paradigm that is based on encoding information in terms of the configuration of charge among quantum dots without requiring current switches. Mostly, QCA cells have been realized by employing the electron switching in square quantum-dot cells. In this paper, a triangular metal-dot cell with a single electron is proposed to represent ternary information. Then, an inverter chain of the proposed triangle cells is suggested through juxtaposing the cells. Additionally, wire crossing and wire fan-out are the two inseparable subjects of QCA wire. A wire-crossing method is presented for the proposed ternary wire. Wire fan-out is also dealt with in this paper by an innovative approach. The correctness of operation of proposed cells and wires are thoroughly verified by applying the physical relations. [ABSTRACT FROM AUTHOR]

Nanomagnetic logic (NML) has recently been proposed as an attractive and promising implementation of QCA and also as a possible alternative to the CMOS technology. With this emerging technology, it is possible to process and store binary information according to the magnetization state of nanomagnets. Similar to other nanotechnologies, NML circuits are also sensitive to fabrication variations and thermal fluctuations. Therefore, it is highly consequential to improve the testability of these circuits. Circuits based on conservative logic inherently enhance test performance. In this paper, the Fredkin gate, which is one of the most famous conservative reversible gates has been designed and simulated in NML by considering the physical properties of nanomagnets. It can be used to design other testable and ultra-low-power NML circuits as well. OOMMF physical simulation tool is used to simulate and validate the proposed gate at room temperature. The results indicate the correct functionality of the design. [ABSTRACT FROM AUTHOR]

Multiple-valued logic (MVL) can lead to fewer interconnections inside and outside a chip. It can also increase computational performance. Despite these intrinsic advantages, MVL circuits are more prone to noise than the binary counterparts. Since the voltage range is divided into some narrow zones, it is essential to consider noise margins carefully when designing MVL circuits in order to make certain of their suitability and adequate reliability. Several ternary and quaternary inverters, whose voltage transfer characteristics (VTC) suffer from reduced noise margins, have been presented in the literature. This shows that further clarification is definitely required. In this paper, the correct VTC curve of a ternary inverter with proper attributes is clarified. The explanations go beyond ternary logic to cover quaternary and other MVL systems as well. Then, the paper undertakes a review of noise margin and static noise margin measurements for some well-known ternary and quaternary inverters. Besides, the effects of process variation on noise margin are studied. [ABSTRACT FROM AUTHOR]

In recent decades, complementary metal–oxide–semiconductor (CMOS) downscaling has faced some serious challenges such as undesired leakage current densities and high power dissipation. One of the most attractive and promising alternative technologies to CMOS is nanomagnetic logic (NML), which is based on nonvolatile ferromagnetic computing states. In this paper, a novel full adder cell is suggested by providing a feedback loop to a special multilayer nanomagnetic majority voter, which switches between three- and five-input majorities periodically. This solution also represents an example revealing the potential of NML for circuit designs that are not accessible using other technologies such as CMOS or quantum-dot cellular automata (QCA). This capability comes from the combination of a clocking system and the nonvolatile behavior of NML. The correct operation of the new full adder cell is verified using the MQCA Verilog library. Comparisons with other state-of-the-art full adders show significant improvements in terms of density and simplicity. [ABSTRACT FROM AUTHOR]

Quantum-dot cellular automata (QCA) circuits are not based on transistors. Therefore, novel concepts and methodologies are required to be able to design Boolean functions in a systematic manner. Wire crossing is a problematic challenge in this technology, imposing considerable cost, complexity, and noise sensitivity. On the other hand, QCA circuits with multiple successive majority gates experience long delays. This paper deals with both problems. At first, some new diagrams are presented for the 13 standard functions, which are sufficient to represent all of the three-input Boolean functions. Some of the standard functions are designed with much fewer wire crossings in this paper compared with the previous designs. Then, with the aim of reducing delay, hierarchical multiplexers are merged together in order to generate wide Boolean functions with fewer layers of majority gates. Circuit compactness is based on some new merging rules. [ABSTRACT FROM AUTHOR]

This paper presents two new 4:2 compressors based on capacitive multi-threshold threshold logic (MTTG), and Carbon Nanotube Field Effect Transistors (CNFETs). The entire capacitor network is divided into two groups in one of the proposed designs. As a result, the number of voltage levels is reduced and the entire structure becomes less sensitive to Process, Voltage, and Temperature variations in comparison with other similar capacitive Threshold Logic (TL) circuits. All designs are simulated by Synopsys HSPICE and 32 nm CNFET technology in different situations and conditions. Simulation results demonstrate the superiority of the second proposed design. It operates 55.9% faster and consumes about 7.2% less power than the second best TL structure (CSTFA). It also operates 16.2% faster and consumes 13.6% less energy in comparison with a traditional design (BLG). Moreover, estimations show that the first proposed design occupies the least area among the capacitive TL circuits. [ABSTRACT FROM AUTHOR]