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Graphene is a promising material for applications as a channel in graphene field-effect transistors (GFETs) which may be used as a building block for optoelectronics, high-frequency devices and sensors. However, these devices require gate insulators which ideally should form atomically flat interfaces with graphene and at the same time contain small densities of traps to maintain high device stability. Previously used amorphous oxides, such as SiO2 and Al2O3, however, typically suffer from oxide dangling bonds at the interface, high surface roughness and numerous border oxide traps. In order to address these challenges, here we use 2 nm thick epitaxial CaF2 as a gate insulator in GFETs. By analyzing device-to-device variability for about 200 devices fabricated in two batches, we find that tens of them show similar gate transfer characteristics. Our statistical analysis of the hysteresis up to 175oC has revealed that while an ambient-sensitive counterclockwise hysteresis can be present in some devices, the dominant mechanism is thermally activated charge trapping by border defects in CaF2 which results in the conventional clockwise hysteresis. We demonstrate that both the hysteresis and bias-temperature instabilities in our GFETs with CaF2 are comparable to similar devices with SiO2 and Al2O3. In particular, we achieve a small hysteresis below 0.01 V for equivalent oxide thickness (EOT) of about 1 nm at the electric fields up to 15 MV cm−1 and sweep times in the kilosecond range. Thus, our results demonstrate that crystalline CaF2 is a promising insulator for highly-stable GFETs. [ABSTRACT FROM AUTHOR]

Recent advances in fabricating field-effect transistors with MoS2 and other related two-dimensional (2D) semiconductors have inspired the industry to begin with the integration of these emerging technologies into FAB-compatible process flows. Just like in the lab research on 2D devices performed in the last decade, focus during development is typically put on pure technology-related issues, such as low-temperature growth methods of large-area 2D films on target substrates, damage-free transfer from sacrificial substrates and growth of top-gate oxides. With maturing technology, the problem of stability limitations caused by oxide traps is gradually coming into focus now. Thus, here we report an in-depth analysis of hysteresis and bias-temperature instabilities for MoS2 FETs fabricated using a 300 mm FAB-compatible process. By performing a comprehensive statistical analysis on devices with top gate lengths ranging between 18 nm and 10 μm, we demonstrate that aggressive scaling results in additional stability problems, likely caused by defective edges of the scaled top gates, in particular at higher operation temperatures. These are important insights for understanding and addressing the stability limitations in future nanoscale 2D FETs produced using FAB process lines. [ABSTRACT FROM AUTHOR]

A new reflected shock tunnel capable of generating hypersonic environments at realistic flight enthalpies has been commissioned at Sandia. The tunnel uses an existing free-piston driver and shock tube coupled to a conical nozzle to accelerate the flow to approximately Mach 9. The facility design process is outlined and compared to other ground test facilities. A representative flight-enthalpy condition is designed using an in-house state-to-state solver and piston dynamics model and evaluated using quasi-1D modeling with the University of Queensland L1d code. This condition is demonstrated using canonical models and a calibration rake. A 25-cm core flow with 4.6-MJ/kg total enthalpy is achieved over an approximately 1-ms test time. The condition was refined using analysis and a heavier piston, leading to an increase in test time. A novel high-speed molecular tagging velocimetry method is applied using in situ nitric oxide to measure the freestream velocity of approximately 3016 m/s. Companion simulation data show good agreement in exit velocity, pitot pressure, and core flow size. [ABSTRACT FROM AUTHOR]

Abstract: The effect of the geometric parameters of Fin field-effect transistors (FinFETs) on hot-carrier degradation (HCD) in these devices is theoretically studied. To this end, a model is used, in which three subproblems constituting the physical phenomenon of HCD are considered: carrier transport in semiconductor structures, description of microscopic defect formation mechanisms, and simulation of degraded device characteristics. An analysis is performed by varying the gate length, fin width and height. It is shown that HCD becomes stronger under fixed stress conditions in transistors with shorter channels or wider fins, while the channel height does not substantially affect HCD. This information can be important for optimizing the architecture of transistors with the fin-shaped channel to suppress degradation effects. [ABSTRACT FROM AUTHOR]

Abstract: For the first time, hot-carrier degradation (HCD) is simulated in non-planar field-effect transistors with a fin-shaped channel (FinFETs). For this purpose, a physical model considering single-carrier and multiple-carrier silicon-hydrogen bond breaking processes and their superpositions is used. To calculate the bond-dissociation rate, carrier energy distribution functions are used, which are determined by solving the Boltzmann transport equation. A HCD analysis shows that degradation is localized in the channel region adjacent to the transistor drain in the top channel-wall region. Good agreement between the experimental and calculated degradation characteristics is achieved with the same model parameters which were used for HCD reproduction in planar short-channel transistors and high-power semiconductor devices. [ABSTRACT FROM AUTHOR]

A detailed simulation of degradation (caused by hot charge carriers) based on self-consistent consideration of the transport of charge carriers and the generation of defects at the SiO/Si interface is carried out for the first time. The model is tested using degradation data obtained with decananometer n-type-channel field-effect transistors. It is shown that the mutual influence of the above aspects is significant and their independent simulation gives rise to considerable quantitative errors. In calculations of the energy distribution for charge carriers, the actual band structure of silicon and such mechanisms as impact ionization, scattering at an ionized impurity, and also electron-phonon and electron-electron interactions are taken into account. At the microscopic level, the generation of defects is considered as the superposition of single-particle and multiparticle mechanisms of breakage of the Si-H bond. A very important applied aspect of this study is the fact that our model makes it possible to reliably assess the operating lifetime of a transistor subjected to the effects of 'hot' charge carriers. [ABSTRACT FROM AUTHOR]

The Boltzmann transport equation is commonly considered to be the best semi-classical description of carrier transport in semiconductors, providing precise information about the distribution of carriers with respect to time (one dimension), location (three dimensions), and momentum (three dimensions). However, numerical solutions for the seven-dimensional carrier distribution functions are very demanding. The most common solution approach is the stochastic Monte Carlo method, because the gigabytes of memory requirements of deterministic direct solution approaches has not been available until recently. As a remedy, the higher accuracy provided by solutions of the Boltzmann transport equation is often exchanged for lower computational expense by using simpler models based on macroscopic quantities such as carrier density and mean carrier velocity. Recent developments for the deterministic spherical harmonics expansion method have reduced the computational cost for solving the Boltzmann transport equation, enabling the computation of carrier distribution functions even for spatially three-dimensional device simulations within minutes to hours. We summarize recent progress for the spherical harmonics expansion method and show that small currents, reasonable execution times, and rare events such as low-frequency noise, which are all hard or even impossible to simulate with the established Monte Carlo method, can be handled in a straight-forward manner. The applicability of the method for important practical applications is demonstrated for noise simulation, small-signal analysis, hot-carrier degradation, and avalanche breakdown. [ABSTRACT FROM AUTHOR]

An approach toward simplification of the model of the tunneling transport of electrons through a thin layer of crystalline calcium fluoride into a silicon (111) substrate with subsequent implementation in simulators of semiconductor devices is suggested. The validity of the approach is proven by comparing the results of modeling using simplified formulas with the results of precise calculations and experimental data. The approach can be applied to calculations of tunneling currents in structures with any crystalline insulators on Si (111). [ABSTRACT FROM AUTHOR]

We model the main characteristics of metal-insulator-silicon field-effect transistors (MISFETs) with different gate insulators using the carrier energy distribution function calculated with a Spherical Harmonics Expansion method. In addition to standard devices with Silicon Dioxide or Oxynitride we study a hypothetical MISFET with a rather new crystalline dielectric-Calcium Fluoride. The real physical parameters of the $$\hbox {CaF}_{2}$$ /Si tunnel barrier are used in our simulations. The obtained characteristics of the transistors with $$\hbox {CaF}_{2}$$ are, in some details, better than those of the devices with traditional oxides. Being a step forward in the context of the industrial implementation of fluorite, this work opens the possibility of simulating the characteristics of different silicon-based devices with crystalline insulators. [ABSTRACT FROM AUTHOR]

We discuss a novel approach to predict non-radiative multi phonon (NMP) transition rates for oxide defects in semiconductor devices in the context of device reliability. In accordance with NMP theory, the influence of the atomic vibration on the electronic transition is assumed to be fully described by the line shape function. This line shape is calculated from density functional theory for a given defect structure and then combined with the carrier spectrum from a non-equilibrium Green's function model of the semiconductor device. Hole capture rates at different temperatures and bias conditions are computed for two well-studied defect structures, the oxygen vacancy and the hydrogen bridge, at different positions in the oxide of an MOS structure. [ABSTRACT FROM AUTHOR]

When applied to partially depleted SOI MOSFETs, the energy transport model predicts anomalous output characteristics. The effect that the drain current reaches a maximum and then decreases is peculiar to the energy transport model. It is not present in drift-diffusion simulations and its occurrence in measurements is questionable. The effect is due to an overestimation of the diffusion of channel hot carriers into the floating body. A modified energy transport model is proposed which describes hot carrier diffusion more realisticly and allows for proper simulation of SOI MOSFETs. [ABSTRACT FROM AUTHOR]