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In this paper, the design and simulation results of a general-purpose fuzzy logic controller, 5-bit digital inputs, and analog output are presented. Based on a new strategy, it provides simplicity and high speed from the analog prospective and a total digital system advantages with unchanged digital system properties. A novel and reliable structure with respect to other topologies for the fuzzifier section is designed which enhances the accuracy and the velocity. In order to detect maximum, minimum, and mixed mode (both minimum and maximum) of the input voltages at the same time, an inference engine consisting of a min and max circuit is an addition. The benchmark for the defuzzifier in the proposed design is simplicity and through a simple approach, and the center of area is attributed to the defuzzifier. The proposed controller circuit consists of two inputs, nine rules and one output designed in TSMC standard 0.18 µm CMOS technology and simulated with MATLAB systematically. The total controller circuit is simulated with HSPICE simulator (BSIM3v3 parameters), and the layouts were extracted with Cadence Virtuoso v 5.1. The whole chip area is less than 0.7 mm2, inference speed of the controller is about 39.2 MFLIPS (fuzzy logic inference per second), and the average power consumption is 2.61 mW. [ABSTRACT FROM AUTHOR]

A simple energy-efficient switching procedure is proposed to reduce the total number of switches and facilitate the capacitors matching requirements in SAR ADCs. The main idea is that the coupling capacitor (CC) is utilized as the same as the unit one, which is applied for LSB charge production. After the reset phase, only the MSB capacitor is connected to the input potential, while the other experience either low and high reference potential; hence, a simplified switching strategy with 55% reduction in number of switches is retrieved. Post-layout simulation results confirm SNDR and ENOB of around 80 dB and 13 bit, respectively, at Nyquist input frequency when the conversion rate is 17 MS/s. In these conditions, FOMW and FOMS reach to 139.9 fJ/Conv-Step and 166.15 dB, respectively. Also, INL and DNL would experience the maximum level of + 0.95/− 0.58 LSB and + 0.63/− 0.74 LSB, respectively. The proposed ADC occupies active area of 1.7 mm2 and consumes around 20.6 mW power at 5 V supply and 17 MS/s conversion rate. Post-layout simulation results are performed using the HSPICE BSIM3 model of a 0.50 µm CMOS process. [ABSTRACT FROM AUTHOR]

This paper presents a new gain stage for high accuracy and fast settling applications. In the proposed structure a novel combination of closed loop and open loop amplifiers is employed to achieve high accuracy and enhanced settling behavior while adding only negligible power to the main circuit power constraint. To evaluate the functionality of the proposed idea, a zero cross based circuit and a switch capacitor amplifier are designed to implement the open loop and the closed loop stages, respectively. Though, other topologies for implementation of open loop and closed loop amplifiers are applicable in the presented gain stage. The proposed structure is implemented in 0.18 μm CMOS technology. HSPICE simulation results, using level 49 models, demonstrate that the new configuration improves the power efficiency and the settling behavior as well as the system accuracy. The proposed scheme shows very fast settling times of 0.8, 1.01, 1.41 ns for the gain accuracies of 6, 8 and 10 bits, respectively, while loaded with 1 pF capacitance and the output swing is 1.6 V. In comparison with a conventional switched capacitor closed loop amplifier, the proposed architecture improves the settling performance by a factor of 3 for 6 bit resolution, while it adds only 0.63 mW power to the total power consumption that is 8.68 mW. [ABSTRACT FROM AUTHOR]

This paper presents an improved bottom-plate sampling sample-and-hold (S/H) architecture for high speed and high linearity analog to digital converters (ADCs). The proposed circuit reduces the charge injection employing a switch at the S/H's output. The S/H circuit has been laid out in 0.35 um CMOS technology and simulated using standard level 49 SPICE parameters. The simulation result shows that the spurious free dynamic range (SFDR) of 80 dB is achieved up to the sampling frequency of 250 MS/s at nyquist input frequency with 1.6 $$(V_{P-P})$$ differential output swing which is able to realize an ADC of 14-bits resolution. [ABSTRACT FROM AUTHOR]

An open loop high speed CMOS differential source follower buffer with improved linearity and negligible extra power consumption in comparison to conventional one is presented. The conventional linear buffers which are commonly implemented in closed loop structure limits the maximum achievable frequency. On the other hand, linearity of differential open loop buffers (source followers) is restricted due to the third harmonic distortion. The proposed differential source follower buffer improves linearity by directly neutralizing third harmonic distortion. Also, a strict analysis on the third harmonic distortion is organized which confirms considerable linearity improvement. The new buffer achieves 86 dB linearity for a 100 MHz 1.6 Vp-p output amplitude, with 2 pF load capacitor at each side in other wise 77 dB linearity of conventional buffer, 95 dB linearity for a 100 MHz 1.0 Vp-p output amplitude in other wise 85 dB linearity of conventional one and 84 dB linearity at dual-tone input frequency in other wise 74.7 dB linearity of conventional one. The power consumption of the proposed buffer is 48 mw while the conventional buffer consumes 42 mw which means about 14 % increases in power consumption leads to 10 dB linearity improvement. The buffer is implemented by using 0.35 μm dual-poly quadruple metal CMOS technology. [ABSTRACT FROM AUTHOR]

In this paper a novel structure is presented as a voltage comparator, and a reliable offset cancellation technique is utilized as well. Moreover a comprehensive post layout simulation method is described to evaluate a vast verity of comparators in order to find out whether the designed structure will operate properly in the post fabrication (solid state) tests or not. A single stage architecture with a simple readout circuit leads to a low-offset low-power high-speed high-resolution comparator which qualifies for VLSI applications such as image sensors. Applying the reliable offset cancellation technique makes it qualified for high performance applications like high-speed high-resolution ADCs. The proposed comparator is simulated through the mentioned method in 0.18 µm standard CMOS technology, and 0.5 mV of accuracy in 1 G sample per second is obtained with a power consumption of 110 µW (150 µW with offset cancellation circuit) where an introduced offset of about 10 mV is cancelled to lower than 220 µV as well. [ABSTRACT FROM AUTHOR]

In this paper a CMOS current-mode analog multiplier circuit based on a novel current-mode squarer circuit is proposed. The circuit is simulated using HSPICE simulator and designed in 0.35 µm standard CMOS technology with ± 1.5 V supply voltage. The simulation results of proposed multiplier for input current range of ±10 μA demonstrate a −3 dB bandwidth of 24.5 MHz, 475 μW as maximum power consumption, nonlinearity of 1.3 % and a THD of 0.87 % at 1 MHz. [ABSTRACT FROM AUTHOR]

This paper presents a novel structure for implementing rational-powered membership functions (RPMFs), which are the extended forms of triangular/trapezoidal membership functions and those functions which are generated by applying linguistic hedges. The hardware realization of an RPMF consists of a triangular membership function generator circuit followed by a rational-powered generator module (RPGM). A novel fully programmable compact triangular/trapezoidal/s-shaped/z-shaped membership function generator with the ability to continuously change parameters is presented which is compatible with the proposed RPGM. A new method is introduced to implement the RPGM based on the approximation of the function ' x' by the functions square and square-rooter which are simply implemented in a current-mode analog approach based on the translinear principle, which leads to a design that is simple, and has high accuracy and less hardware usage, with a resulting lower chip area and lower power consumption. The designed circuit was simulated by an HSPICE simulator with level 49 parameters (BSIM3v3), and the simulation results show that the maximum power consumption of the RPGM is 800 μW, while the maximum RMS error is 1.25 %. Finally, layouts of the circuits prepared using Cadence software are presented. [ABSTRACT FROM AUTHOR]

The basic bandgap reference voltage generator, BGR, is thoroughly analyzed and relations are reconstructed considering dependency of bandgap energy, E, to absolute temperature. The previous works all consider E as a constant, independent of temperature variations. However, E varies around 25 meV when the temperature is increased from 2 to 92 °C. In this paper the dependence of E to absolute temperature, based on HSPICE mosfet models in HSPICE MOSFET Models Manual (Version X-2005.09, ), is approximated by a third-order polynomial using Lagrangian interpolating method within the temperature range of 2-92 °C. Accurate analysis on the simplified polynomial reveals that the TC of V must be corrected to −1.72 mV/°K at 27 °C which has been formerly reported about −1.5 mV/°K in Razavi (Design of analog CMOS integrated circuits, ) and Colombo et al. (Impact of noise on trim circuits for bandgap voltage references, ), −2 mV/°K in Gray et al. (Analysis and design of analog integrated circuits, ), Leung and Mok (A sub-1-V 15-ppm/°C CMOS bandgap voltage reference without requiring low threshold voltage device, ), Banba et al. (A CMOS bandgap reference circuit with sub-1-V operation, ), and −2.2 mV/°K in Jones and Martin (Analog integrated circuit design, ), Tham and Nagaraj (A low supply voltage high PSRR voltage reference in CMOS process, ). Another important conclusion is that the typical weighting coefficient of TC+ and TC− terms is modified to about 19.84 at 27 °C temperature from otherwise 16.76, when E is considered constant, and also 17.2, in widely read literatures, (Razavi in Design of analog CMOS integrated circuits, ). Neglecting the temperature dependence of E might introduce a relative error of about 20.5 % in TC of V. Also, resistance and transistor size ratios, which denote the weighting coefficient of TC+ term, might be encountered to utmost 20.3 % error when the temperature dependence of E is ignored. [ABSTRACT FROM AUTHOR]

A new open loop, high resolution CMOS sample and hold (S/H) circuit is introduced in this article. This circuit is constructed based on a new method which leads to a great reduction in dependency of the storing charge of the holding capacitors to the charge injection of transistors. It is a combination of dummy switches and auxiliary capacitors in order to decrease the voltage spikes that are produced during the sampling mode. Due to the high linearity feature of our proposed design in comparison with previous works, it is reached to a great improvement in signal to noise and distortion ratio up to about 15 dB and it's ENOB is equivalent with about 16 bits. Another advantages of our proposed design are it's lower power dissipation and it's high input voltage range. Also the optimum functionality of our proposed circuit does not damaged by the threshold voltage's variations in different corners. As our proposed S/H circuit has been designed in open loop structure, it is suitable for high speed applications. [ABSTRACT FROM AUTHOR]

As threshold voltage of CMOS transistors is the main parameter that takes effect from process variations, in this paper a novel method for corner detection is presented which senses the variations of fabrication process through threshold voltage of the devices. A new general purpose 2-input, 2-output, 25 rules, ANFIS based fuzzy controller is proposed to compensate the variations subsequently. In this controller novel structures are presented for each block including membership function generator, Min-Max selector and defuzzifier. As an application, bias points of comparators of a typical flash ADC are controlled through introduced system in order to compensate the process variation effects and minimizing total power consumption consequently. Due to differential structures used in the architecture of the blocks, major part of the power supply noise is rejected. The Hspice (level 49) simulation results are given using a generic 0.35 μm standard CMOS technology parameters and power supply of 3.3 V with total power consumption of 15.6 mW for 7.4 MFLIPS. Because of simple and symmetrical circuitry, layout of the proposed controller is very compact, about 410 μm × 210 μm. [ABSTRACT FROM AUTHOR]

In this article, a fully programmable membership function generator (MFG) is proposed. This MFG is capable of generating triangular, trapezoidal as well as both S-shaped and Z-shaped membership functions simultaneously. Utilizing a differential pair as an analog switch leads to relax the design of fuzzy systems control part. This MFG has the ability of adapting itself with various fuzzy controllers which produce different control voltage ranges. Unlike the available reported literatures, this MFG uses a new analog programmable current mirror (APCM) instead of digitally programmable current mirrors to adjust the slopes of membership functions. Extensive time domain simulations have been carried out using Hspice by level 49 parameters (BSIM3v3) in standard CMOS technology to validate the effective performance of the proposed MFG. [ABSTRACT FROM AUTHOR]

In this article, a 3.2 Gb/s serial link transceiver, that can be implemented in 0.35 μm CMOS technology is presented. In this transceiver a new multi-level pulse-width-amplitude modulation technique is used. The symbol rate is reduced, while the minimum pulse width (PW) is increased considerably, using the proposed modulation. The PW is larger than the conventional NRZ data format, with PW of Tb, so the ISI will be improved. The multiphase output of a three stage ring oscillator VCO in the PLL is used to modulate and to demodulate the signal. A new charge pump circuit is also introduced to decrease the mismatch between up and down paths. The peak to peak jitter of recovered clock is 21 ps at 800 MHz. The recovered data has the peak to peak jitter of 51 ps. The transmitter and receiver power consumption is 220 and 35 mW, respectively. [ABSTRACT FROM AUTHOR]

In this paper a new operational amplifier is presented based on the conventional folded cascode Op-Amp structure. A new method of positive feedback is used to increase DC-gain. Contrary to conventional designs this method does not decrease the speed of the folded cascode Op-Amp in the closed loop configuration. Simplicity is the other advantage of the proposed Op-Amp in comparison with the conventional structures. In this method, DC-gain improves by adding only two devices to the folded cascode structure. The additional devices neither decrease the bandwidth nor increase the power consumption, to a great extent. Proposed structure has been simulated by HSPICE software using level 49 parameters ( BSIM3v3) in a typical 0.35 μm CMOS technology. HSPICE simulation confirms the theoretical estimated improvements. [ABSTRACT FROM AUTHOR]

In this paper a new operational amplifier is presented which is based on the conventional folded cascode Op-Amp structure. A new method of positive feedback is used to increase dc-gain. This method does not limit the range of the output voltage swing. True performance of the Op-Amp in higher output voltage swings is another advantage of the proposed Op-Amp in comparison with the conventional structures. Bulk amplification and positive feedback are used to improve the Op-Amp specifications. Proposed structure has been simulated by HSPICE software using level 49 parameters (BSIM3v3) in a typical 0.35 μm CMOS technology. The HSPICE simulation confirms the theoretical estimated improvements. [ABSTRACT FROM AUTHOR]

This paper proposes the method to implement a general form of membership functions for fuzzy systems in CMOS technology. These membership functions are a general form of triangular types and those functions which are used in linguistic hedge fuzzy logic, hence can offer better performance in almost all applications. The comparison between the proposed method and previously reported works shows better performance in all parameters. Designed circuits to implement these types of membership functions are simulated using HSPICE by level 49 parameters (BSIM3v3) in 0.35 μm standard CMOS technology. Current mode realization of the circuits leads to simple and intuitive configurations. The Rational Power Generator Module (RPGM) generates powers with the resolution of 0.03125 and using seven programming bits. The simulation results of RPGM demonstrate a RMS error of 1.42% and a maximum power consumption of 1.05 mW. [ABSTRACT FROM AUTHOR]