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This paper presents a new ultra-low power double-tail latched comparator suited for biomedical applications. The proposed comparator benefits from a positive feedback to achieve high resolution with low kickback noise. It is shown by time analysis and simulation that the delay time is significantly reduced compared to a conventional double-tail latched comparator. The presented circuit is designed and simulated in 0.18-μm CMOS technology. The post-layout simulation results show that the designed comparator consumes only 1.56 nW power, at 600 mV supply voltage and 100 kHz clock frequency. This amount is 54.35 % of power consumption of a conventional double-tail latched comparator with the same input referred offset of 7.5 mV. Furthermore, the proposed circuit provides a self-neutralization technique which results 8.8 % reduction of kick-back noise in comparison to the conventional latched comparator. The maximum clock frequency of this circuit is 200 MHz at 1 V supply voltage. The proposed circuit has a power-delay product of 0.0172 fJ at 100 kHz clock frequency. The proposed comparator is well designed to operate with supply voltages between 400 mV and 1 V. [ABSTRACT FROM AUTHOR]

A blind watermarking technique based on QR decomposition is proposed on still images. The method is presented in spatial as well as transform domains and its robustness against some well-known image processing attacks is evaluated. It is shown that the QR decomposition offers capacity and robustness comparable to or better than similar watermarking based on the DCT and SVD transformations. Also, an interesting property of QR decomposition, which for the first time has been introduced by our previous paper, is proved and put in practice in more details. [ABSTRACT FROM AUTHOR]

A new architecture for successive-approximation register analog-to-digital converters (SAR ADC) using generalized non-binary search algorithm is proposed to reduce the complexity and power consumption of the digital circuitry. The proposed architecture is based on the split capacitive-array DAC with a simple switching logic as compared to the conventional non-binary SAR ADC architecture. A 10-bit 50-MS/s SAR ADC is designed based on the proposed architecture in a 0.18 μm CMOS technology. Simulation results show that at a supply voltage of 1.2 V, the SAR ADC achieves a peak signal-to-noise-and-distortion ratio of 59.5 dB, and a power consumption of 1.3 mW, resulting in a figure of merit of 33 fJ/conversion-step. [ABSTRACT FROM AUTHOR]