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This paper presents a new structure for switched-capacitor multilevel inverter with octuple voltage gain capability. The proposed inverter utilizes three capacitors, 13 semiconductor switches, three diodes, and an input voltage source to achieve a 17-level output voltage. The switched capacitors naturally achieve voltage balancing without the need for sensors or additional circuits, indicating the ease of control of the proposed structure. To control the inrush current of the switched capacitors, a charge limiting inductor has been utilized in the charging path of the capacitors. This not only reduces the inrush current of the capacitors and the input source current but also enables faster capacitor charging and extends their lifetime. The switches used in the proposed structure can withstand a maximum of 4 times the input voltage value or the half of the maximum output voltage, which is a significant advantage for the proposed structure. A detailed comparison with similar structures is provided to examine the advantages and disadvantages of the suggested inverter. The procedure of self-voltage balancing of the capacitors and the functional modes of the proposed topology has been explained in detail. The proposed structure is suitable for applications such as renewable energy sources transfer to load or grid. The performance of the proposed topology under different conditions is confirmed through simulation in the Matlab\Simulink software and the implementation of the laboratory sample. [ABSTRACT FROM AUTHOR]

In this paper, an interleaved DC–DC step-up converter with improved characteristics based on a voltage multiplier rectifier is presented. The proposed converter is presented and analyzed for two different operating duty regions including operating region 1 (0 < D ≤ 0.5), and operating region 2 (0.5 ≤ D < 1). This converter can be used in various applications such as energy storage, electric vehicles, and renewable energy systems. This converter is composed of two stages: an interleaved boost stage and a voltage multiplier rectifier stage, which collectively forms its general structure. The interleaved boost stage is a type of two-phase boost converter that transforms the input DC voltage into a high-frequency AC square waveform. This waveform can be readily filtered using smaller capacitors. The square-shaped voltage waveform from the interleaved boost stage is rectified and converted to a high DC voltage by the Voltage Multiplier Rectifier (VMR) stage. The operating regions, the evaluation of the steady-state condition, the voltage gain of the proposed converter's parasitic and ideal models as well as its losses and efficiency analysis have been evaluated. The proposed converter has an efficiency of 97% at the output power of 150 W. The proposed converter is simulated to convert a voltage of 25–159.5 V and to validate the mathematical relationships and simulation results, a laboratory prototype has been developed. The simulation and experimental results show the precision of the performance of the proposed interleaved boost converter. [ABSTRACT FROM AUTHOR]

In this paper, a quadruple boost switched-capacitor multi-level inverter is proposed. The proposed structure utilizes a DC source, 11 switches, and a diode to achieve 17-level output voltage levels. This structure consists of three capacitors with the ability for self-balancing voltages. The capacitors achieve automatic voltage balancing through a series/parallel connection with the input voltage source. To control the switching pulses of the switches, level-shifted pulse width modulation (LS-PWM) strategy has been employed. A comparative evaluation has been performed between the proposed structure and structures presented in recent articles, considering various parameters such as voltage gain, number of DC sources, number of semiconductor devices, maximum blocking voltage (MBV), and total standing voltage (TSV). Considering this comparison, the lower number of semiconductor devices for generating a 17-level output with suitable voltage gain, and especially the cost-effectiveness of the structure, are the main advantages of the proposed configuration. In addition, a soft charging method has been employed to limit the inrush current of capacitors. Moreover, the power losses of the proposed structure have been investigated, indicating its acceptable efficiency. Finally, for the analysis and validation of the proposed structure's performance, an experimental prototype has been implemented and evaluated under various conditions. The results indicate satisfactory performance of the proposed structure under various stable and dynamic operating conditions. [ABSTRACT FROM AUTHOR]

In this paper, a new topology is introduced for capacitor-based multi-level inverters. The proposed topology is based on combination of two Cross-Square-Switched T-Type inverters. This structure can be generalized in two modular and cascaded modes. In the cascaded mode, higher voltage levels are produced with low power switches. The main features of the proposed topology include the level generation without the utilization of the H-bridge module, the low number of switching components, a lower number of DC voltage sources, and low total blocking voltage. Besides, in the proposed topology, the number of conducting switches in the current path for each different voltage level is low, which leads to a conduction loss decrement. The loss simulations are performed, and the results are presented. A study provides a detailed comparison of the proposed topology in terms of various parameters. In this paper, the nearest level modulation switching, which is low-frequency switching, is utilized to generate voltage levels. To confirm the performance of the proposed topology, a simulation was performed with MATLAB/Simulink software, and a laboratory sample was implemented. Comparative results, simulation results, and implementation results indicate the appropriate performance of the proposed structure in different steady-state and dynamic conditions. [ABSTRACT FROM AUTHOR]

Utilization of small-scale wind energy conversion systems (WECS) has been grown in recent years. Permanent magnet synchronous generator due to lack of slip rings is a suitable alternative for induction generators to be used in these systems. However, these generators use full power converters which means higher power losses. In this paper, an ultra-efficient three-level converter, called T-type converter, is used in a back-to-back configuration as power electronic interface for PMSG-based small-scale WECS. Then, simulations are carried out to evaluate the efficiency of the system and compare it to conventional two- and three-level back-to-back configurations. Meanwhile, thermal analysis is carried out to investigate the thermal loading of different switching components of the converter. Data given by this analysis can be further used to evaluate system reliability. Therefore, system reliability is calculated and compared to conventional two- and three-level converter systems. [ABSTRACT FROM AUTHOR]

In this paper, a novel Cascaded H-Bridge (CHB)-based multilevel inverter for symmetric/asymmetric configurations is presented. The proposed MLI can be utilized in medium-voltage applications such as electrical machine drives as well as grid connection of renewable energy resources. The proposed structure uses fewer count of semiconductor devices at the same voltage level in comparison with classic and advanced structures. Cascaded connection of the proposed basic cells leads to reduce complexity and increase efficiency of the proposed structure. In order to investigate the capability and superiority of the proposed structure, a comprehensive comparison is conducted between this structure and the advanced ones in terms of efficiency, switch and gate driver count, and total blocking voltage (TBV). The fundamental frequency switching method is employed to generate proper switching pulses. The performance of the proposed multilevel inverter is investigated by simulating in MATLAB/Simulink environment. The experimental implementation for proposed 15-level symmetric and 33-level asymmetric structures validates the correctness of simulation results. [ABSTRACT FROM AUTHOR]

Speed control of conventional low-voltage low-power induction motors (LV-LP-IMs) by two-level voltage source inverter (2LVSI) has some difficulties due to limitations of LV-LP-IMs especially insulation system. Besides, the use of multilevel inverters is not cost-effective either. In this paper, the new topology of reduced-switch-count three-level inverter with only eight switches is proposed for speed controlling of LV-LP IM. Eight-switch inverter is a newly three-level converter, which has the fewer number of switching devices, lower cost, smaller volume compared with the conventional three-level inverters, while it has sufficient switching vectors to speed control of IMs. In this paper, the structure and switching vectors of the eight-switch inverter are analyzed, and the direct torque control method based on the switching table and voltage balancing of the DC input voltage are presented for the LV-LP-IM speed control. Simulation results, considering different work conditions, are presented in order to validate finally the good performance of the proposed method. Moreover, the obtained results are compared with 2LVSI and conventional three-level inverters in different aspects. [ABSTRACT FROM AUTHOR]