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Bicubic interpolation is a classic algorithm in the real-time image processing systems, which can achieve good quality at a relatively low hardware cost, and is also the fundamental component of many other much more complex algorithms. However, the multiply-accumulate units (MAC) in the bicubic require massive resources in the hardware-based implementation, which limits the use of the bicubic algorithm. In this article, a hybrid architecture of fix-point and stochastic computing is proposed to reduce the hardware resource consumption by computing the low-weight bits ambiguously. The proposed architecture is tested on standard image sets to survey the performance and is implemented on Intel Cyclone V and Xilinx Virtex-II targets to verify the hardware consumption. The experimental results show that the proposed architecture achieves significant resource reduction and even higher image processing speed compared to the existing architectures with comparable performance. [ABSTRACT FROM AUTHOR]

Sample-timing error can cause significant performance degradation for the interleave-division multiple-access systems (Wang et al. ). In this paper, we propose a non-data-aided timing acquisition scheme to mitigate sample-timing error due to the asynchronous transmission of random allocated user ends (UEs) on the uplink. A closed-loop timing control scheme is constructed for the asynchronous IDMA system in this paper. We use the extrinsic information generated during the iterative detection algorithm with signal noise ratio evolution to estimate the timing offset for the asynchronous uplink in the base station (BS) receiver. The BS receiver returns the timing control bits, which is generated with estimated timing offsets, to the corresponding UE. And the UE uses the timing control bits to adjust local transmission time to guarantee the sampling performance at the BS receiver. The simulation results show that the proposed acquisition scheme based on feedback loop can provide high acquisition probability and low false alarm probability. The proposed scheme can overcome the bit-error-rate performance bottleneck, which is caused by the sample-timing error in BS receiver due to the asynchronous signals in the uplink. [ABSTRACT FROM AUTHOR]

High efficient implementation of scaling in residue number system (RNS) is one of the critical issues for the applications of RNS in digital signal processing (DSP) systems. In this paper, an efficient scaling algorithm for signed integers in RNS is proposed firstly through introducing a correction constant in negative integers scaling procedure. Based on the proposed scaling algorithm, an efficient RNS 2 n scaling implementation method is presented, in which Chinese remainder theorem (CRT) and a redundant modulus are used to perform the base extension to obtain the least significant n bits of RNS integers. With the redundant modulus, the RNS sign detection can be achieved by the parity detection. And then, an approach to update the residue digit of the redundant channel is also proposed. Meanwhile, this paper provides a method of computing the correction constant of the redundant channel in negative integers scaling. The analysis results indicate that the complexity of the proposed scaling algorithm grows linearly with the word-length of the RNS dynamic range without using Look-up Table (LUT). Furthermore, the proposed algorithm is employed for a specific moduli set 2 n scaling. The synthesis results show that the critical path of the proposed algorithm is shortened by 12%, the area and power consumption performance is improved by about 35%, compared to the existing cascading 2 n scaling method for very large scale integration (VLSI) implementation under the same restriction. Besides, the VLSI layout indicates that the parallel structure is simpler. [ABSTRACT FROM AUTHOR]

Residue number system (RNS) has received considerable attention since decades before, because it has inherent carry-free and parallel properties in addition, subtraction, and multiplication operations. For an odd moduli set, the fundamental problems in RNS, such as number comparison, sign determination, and overflow detection, can be solved based on parity checking. The paper proposes a parity checking algorithm along with related propositions and the certification based on the celebrated Chinese remainder theory (CRT) and mixed radix conversion (MRC) for the moduli set {2 n − 1, 2 n + 1, 22 n + 1}. The parity checker consists of two modular adders and a carry-look-ahead chain. The hardware implementation requires less area and path delay. Besides, the implementations of number comparison, sign determination, and overflow detection, which are based on this parity checker, are also performed in this paper. And this kind of parity checker can be used as a basic element to design ALUs and DSP module in RNS. [ABSTRACT FROM AUTHOR]

A novel memory efficient path metric update is proposed for Maximum A Posteriori (MAP) decoder of turbo codes to reduce the memory requirement of state metric information calculation. For MAP decoder, the same memory can be shared by the forward and backward metrics with this metric update scheme. The forward and backward metrics update can be performed at the same time. And all of the extrinsic information can be calculated at the end of metric update. Therefore, the latency and area in the implementation will be reduced with the proposed metric update method. [ABSTRACT FROM AUTHOR]