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Trapping phenomena degrade the dynamic performance of wide-bandgap transistors. However, the identification of the related traps is challenging, especially in presence of non-ideal defects. In this paper, we propose a novel methodology (trap-state mapping) to extract trap parameters, based on the mathematical study of stretched exponential recovery kinetics. To demonstrate the effectiveness of the approach, we use it to identify the properties of traps in AlGaN/GaN transistors, submitted to hot-electron stress. After describing the mathematical framework, we demonstrate that the proposed methodology can univocally describe the properties of the distribution of trap states. In addition, to prove the validity and the usefulness of the model, the trap properties extracted mathematically are used as input for TCAD simulations. The results obtained by TCAD closely match the experimental transient curves, thus confirming the accuracy of the trap-state mapping procedure. This methodology can be adopted also on other technologies, thus constituting a universal approach for the analysis of multiexponential trapping kinetics. [ABSTRACT FROM AUTHOR]

We present a combined theoretical, numerical and experimental investigation on trap-assisted tunneling (TAT) in the subthreshold regime of III-nitride-based light-emitting diodes (LEDs). Starting from the basic formulation of the TAT models provided by Hurkx and Schenk, we discuss the derivation of a detailed approach based on both multiphonon and elastic nonlocal processes. A sensitivity study conducted over the main trap- and phonon-related physical parameters of this nonlocal TAT model confirms the importance of tunneling assisted by lattice defects on the LED electrical behavior in the low-medium forward bias range. Comparisons with measured temperature-dependent electrical characteristics $$I(V;T)$$ of a single quantum well LED grown on a highly conductive SiC substrate demonstrate that $$I(V;T)$$ can be accurately reproduced in the range between 200 and 400 K by implementing the nonlocal model for TAT processes via traps in the electron-blocking and spacer layers. [ABSTRACT FROM AUTHOR]

The effects of direct-current (DC) stress on GaN high-electron-mobility transistors (HEMTs) are investigated by means of numerical simulations, by which the creation of an acceptor trap in the AlGaN barrier layer was correlated to the observed experimental degradation. An increase in the trap concentration induces a worsening of the saturated current I, transconductance g, and output conductance g. An increase in the length of the trapping region induces a degradation of I and g, but can reduce g. Analysis of scattering parameters in the saturation region shows that the cutoff frequency f matches the trend of g. [ABSTRACT FROM AUTHOR]