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This paper presents a micro power light energy harvesting system for indoor environments. Light energy is collected by amorphous silicon photovoltaic (a-Si:H PV) cells, processed by a switched capacitor (SC) voltage doubler circuit with maximum power point tracking (MPPT), and finally stored in a large capacitor. The MPPT fractional open circuit voltage (V) technique is implemented by an asynchronous state machine (ASM) that creates and dynamically adjusts the clock frequency of the step-up SC circuit, matching the input impedance of the SC circuit to the maximum power point condition of the PV cells. The ASM has a separate local power supply to make it robust against load variations. In order to reduce the area occupied by the SC circuit, while maintaining an acceptable efficiency value, the SC circuit uses MOSFET capacitors with a charge sharing scheme for the bottom plate parasitic capacitors. The circuit occupies an area of 0.31 mm in a 130 nm CMOS technology. The system was designed in order to work under realistic indoor light intensities. Experimental results show that the proposed system, using PV cells with an area of 14 cm, is capable of starting-up from a 0 V condition, with an irradiance of only 0.32 W/m. After starting-up, the system requires an irradiance of only 0.18 W/m (18 μW/cm) to remain operating. The ASM circuit can operate correctly using a local power supply voltage of 453 mV, dissipating only 0.085 μW. These values are, to the best of the authors' knowledge, the lowest reported in the literature. The maximum efficiency of the SC converter is 70.3 % for an input power of 48 μW, which is comparable with reported values from circuits operating at similar power levels. [ABSTRACT FROM AUTHOR]

The pursuit for energy and area efficient circuits has become greater than ever. Low power and small area integrated circuits are in high demand today. Reference voltage circuitry for analog-to-digital conversion comprises 20-30 % of the overall power and area of the ADC. To this end, a fully differential 1.5-bit multiplying digital-to-analog converter (MDAC) precluding reference voltages, that can be employed in MDAC-based ADCs, is presented. Reference shifting is performed in current-mode and the gain of two is obtained by associating charged capacitors in series in the opamp's feedback loop, achieving a unity feedback factor. Theoretical analyses of various nonideal effects of the reference shifting and gain of two are presented and confirmed with electrical level simulations. Furthermore, to avoid reference voltages in the local quantizers, an architecture with built-in thresholds is used. A proof of concept 1.5-bit/stage 7-bit 500 MS/s pipeline ADC is designed using the proposed MDAC in a standard digital 0.13 μm CMOS technology. The ADC achieves a peak SNDR and SFDR of 36.1 and 48.7 dB, respectively, while dissipating 12.7 mW from a single 1.2 V supply voltage, and it does not require external reference circuitry. [ABSTRACT FROM AUTHOR]