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The International Roadmap for Devices and Systems (IRDS) forecasts that, for silicon-based metal–oxide–semiconductor (MOS) field-effect transistors (FETs), the scaling of the gate length will stop at 12 nm and the ultimate supply voltage will not decrease to less than 0.6 V (ref. 1). This defines the final integration density and power consumption at the end of the scaling process for silicon-based chips. In recent years, two-dimensional (2D) layered semiconductors with atom-scale thicknesses have been explored as potential channel materials to support further miniaturization and integrated electronics. However, so far, no 2D semiconductor-based FETs have exhibited performances that can surpass state-of-the-art silicon FETs. Here we report a FET with 2D indium selenide (InSe) with high thermal velocity as channel material that operates at 0.5 V and achieves record high transconductance of 6 mS μm−1 and a room-temperature ballistic ratio in the saturation region of 83%, surpassing those of any reported silicon FETs. An yttrium-doping-induced phase-transition method is developed for making ohmic contacts with InSe and the InSe FET is scaled down to 10 nm in channel length. Our InSe FETs can effectively suppress short-channel effects with a low subthreshold swing (SS) of 75 mV per decade and drain-induced barrier lowering (DIBL) of 22 mV V−1. Furthermore, low contact resistance of 62 Ω μm is reliably extracted in 10-nm ballistic InSe FETs, leading to a smaller intrinsic delay and much lower energy-delay product (EDP) than the predicted silicon limit.A two-dimensional field-effect transistor made of indium selenide is shown to outperform state-of-the-art silicon-based transistors, operating at lower supply voltage and achieving record high transconductance and ballistic ratio. [ABSTRACT FROM AUTHOR]

The inferior electrical contact to two-dimensional (2D) materials is a critical challenge for their application in post-silicon very large-scale integrated circuits. Electrical contacts were generally related to their resistive effect, quantified as contact resistance. With a systematic investigation, this work demonstrates a capacitive metal-insulator-semiconductor (MIS) field-effect at the electrical contacts to 2D materials: The field-effect depletes or accumulates charge carriers, redistributes the voltage potential, and gives rise to abnormal current saturation and nonlinearity. On one hand, the current saturation hinders the devices' driving ability, which can be eliminated with carefully engineered contact configurations. On the other hand, by introducing the nonlinearity to monolithic analog artificial neural network circuits, the circuits' perception ability can be significantly enhanced, as evidenced using a coronavirus disease 2019 (COVID-19) critical illness prediction model. This work provides a comprehension of the field-effect at the electrical contacts to 2D materials, which is fundamental to the design, simulation, and fabrication of electronics based on 2D materials. [ABSTRACT FROM AUTHOR]

Carbon nanotube field-effect transistor (CNT FET) has been considered as a promising candidate for future high-performance and low-power integrated circuits (ICs) applications owing to its ballistic transport and excellent immunity to short channel effects (SCEs). Still, it easily suffers from the ambipolar property, and severe leakage current at off-state originated from gate-induced drain leakage (GIDL) in CNT FETs with small bandgap. Although some modifications on device structure have been experimentally demonstrated to suppress the leakage current in CNT FETs, there is still a lack of the structure with excellent scalability, which will hamper the development of CNT FETs toward a competitive technology node. Here, we explore how the device geometry design affects the leakage current in CNT FETs, and then propose the possible device structures to suppress off-state current and check their availability through the two-dimensional (2D) TCAD simulations. Among all the proposed structures, the L-shaped-spacer CNT FET exhibits significantly suppressed leakage current and excellent scalability down to sub-50 nm with a simple self-aligned gate process. According to the simulation results, the 50 nm gate-length L-shaped-spacer CNT FET exhibits an off-state current as low as approximately 1 nA/µm and an on-current as high as about 2.1 mA/µm at a supply voltage of −1 V and then can be extended as a universal device structure to suppress leakage current for all the narrow-bandgap semiconductors based FETs. [ABSTRACT FROM AUTHOR]

A novel three-dimensional device structure for a carbon nanotube (CNT) fin field-effect transistor (FinFET) is proposed and evaluated. We evaluated the potential of the CNT FinFET compared with a Si FinFET at a 22-nm node at the circuit level using three performance metrics including propagation delay, total power dissipation, and energy-delay product (EDP). Compared with a Si FinFET, the CNT FinFET presents obvious advantages in speed and EDP arising from its almost much larger current density but also results in a higher total power dissipation, especially at a low threshold voltage ( V = 1/3 V ). A suitable improvement in V can effectively contribute to a significant suppression of leakage current and power dissipation, and then an obvious optimization is obtained in the EDP with an acceptable sacrifice in speed. In particular, CNT FinFETs with optimized threshold voltages can provide an EDP advantage of approximately 50 times over Si FinFETs under a low supply voltage ( V = 0.4 V), suggesting great potential for CNT FinFET-based integrated circuits. [ABSTRACT FROM AUTHOR]

The speed of frequency response of all published carbon nanotube (CNT) integrated circuits (ICs) is far from that predicted. The transient response of CNT ICs is explored systematically through the combination of experimental and simulation methods. Complementary field-effect-transistor (FET) based inverters were fabricated on a single semiconducting CNT, and the dynamic response measurement indicates that it can only work at an unexpectedly low speed, i.e. with a large propagation delay of 30 μs. Owing to the larger output resistance of CNT FETs, the existence of parasitic capacitances should induce much larger resistive-capacitive (RC) delay than that in Si ICs. Through detailed analysis combining simulation and experimental measurements, several kinds of parasitic capacitances dragging down the actual speed of CNT FET ICs are identified one by one, and each of them limits the speed at different levels through RC delay. It is found that the parasitic capacitance from the measurement system is the dominant one, and the large RC delay lowers the speed of CNT FETs logic circuits to only several kHz which is similar to the experimental results. Various optimized schemes are suggested and demonstrated to minimize the effect of parasitic capacitances, and thus improve the speed of CNT ICs. [Figure not available: see fulltext.] [ABSTRACT FROM AUTHOR]

The article Field-effect at electrical contacts to two-dimensional materials, written by Yao Guo et al., was erroneously originally published electronically on the publisher's internet portal (currently SpringerLink) on 28 July 2021 with Ref. [27] and Table of contents. [ABSTRACT FROM AUTHOR]