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The use of distributed loop buffer architectures with incompatible loop-nest organisations allows the execution of incompatible loops in parallel with minimal hardware overhead. Due to this fact, the utilisation of these distributed and scalable architectures in embedded systems is a promising option to improve the energy efficiency of the instruction memory organisations that exist in these systems. This paper proposes and analyses non-overlapping and complementary implementation options for distinct partitions of the design space that is related to distributed loop buffer architectures. The high-level trade-off analysis of the proposed implementations is crucial to present the correct process design that an embedded systems designer has to follow in order to have an efficient distributed loop buffer architecture for a certain application. Results show that, with an increase of about 6.5 % in the energy consumption of the control logic that exists in the instruction memory organisation, the overall energy consumption of the instruction memory organisation can be reduced by 6 % to 22 %, when distributed loop buffer architectures with incompatible loop-nest organisations are used instead of clustered loop buffer architectures with shared loop-nest organisations architectures. [ABSTRACT FROM AUTHOR]

Next generation mobile wireless systems (4G) support a wide range of communication protocols and services, thus opening new design challenges. The desired flexibility requires an effective utilization of system resources. In this article, we introduce the concept of system scenarios in wireless baseband engine signal processing optimization and in digital front-end power optimization. The scenario methodology classifies the system behavior from a cost perspective and provides the necessary information for an effective system tuning. We propose improvements for the clustering of the system executions into scenarios and the detection of scenarios at run time achieving a better trade-off between cost estimation accuracy and detection overhead. The first case study of the paper, using the WLAN communication protocol, demonstrates the accurate prediction of the execution time of each block of bits, which on average is 92 % shorter than the worst case allowing us to use the remaining time for the optimization of specifications like power consumption. In the second case study, we concentrate on the efficient signal power management during a WLAN transmission reducing the total energy consumption 50-94 % based on the throughput utilization. [ABSTRACT FROM AUTHOR]

Novel cognitive radio platforms, such as IMEC's COgnitive Baseband RAdio (COBRA), should ensure the feasibility of multiple streams and their reconfigurability and scalability during run-time. The control over these tasks should be dedicated to a run-time controller that (re)allocates the resources on the platform. E.g., when the channel conditions change requiring a switching to different modulation and coding scheme or a user starts a new stream. Current transaction level models are too detailed for rapid exploration of all run-time options and the high-level data-flow frameworks (such as Kahn process networks) lack the dynamism and reconfigurability that is essential for the exploration. In this paper we propose the DAtaflow for Run-Time (DART), the high-level dynamic data-flow platform model framework, suited for rapid run-time control development. We sketch how to use this framework to develop such a controller in the reactive and more challenging, proactive way. We derive the component timing based on Instruction Set Simulator (ISS) simulation and the reconfiguration timing based on Transaction Level Modeling (TLM) simulation. Finally, we verify results of our DART approach with full TLM simulation of our platform. [ABSTRACT FROM AUTHOR]

Emerging Software Defined Radio (SDR) baseband platforms are based on multiple processors with massive parallelism. Although the computational power of these platforms would theoretically enable SDR solutions with advanced wireless signal processing, existing work implements still rather basic algorithms. For instance, current Multiple-Input Multiple-Output (MIMO) detector implementations are typically based on simple linear hard-output and not on advanced near-Maximum Likelihood (ML) soft-output detection. However, only the latter enables to exploit the full potential of MIMO technology. In this work, we explore the feasibility of advanced soft-output near-ML MIMO detectors on massive parallel processors. Although such detectors are considered to be very challenging due to their high computational complexity, we combine architecture-friendly algorithm design, application specific instructions and instruction-level/data-level parallelism explorations to make SDR solutions feasible. We show that, by applying the proposed combination of techniques, it is possible to obtain SDR implementations which can deliver data rates that are sufficient for future wireless systems. For example, a 2 × 4 Coarse Grain Array (CGA) processor with 16-way Single Instruction Multiple Data (SIMD) can deliver 192/368 Mbps throughput for 2 × 2 64/16-QAM transmissions. Finally, we estimate the area and power consumption of the programmable solution and compare it against a traditional Application Specific Integrated Circuit (ASIC) approach. This enables us to draw conclusions from the cost perspective. [ABSTRACT FROM AUTHOR]

This paper presents a memory organization for SDR inner modem baseband processors that focus on exploiting ILP. This memory organization uses power-efficient, single-ported, interleaved scratch-pad memory banks to provide enough bandwidth to a high-ILP processors. A system of queues in the memory interface is used to resolve bank conflicts among the single-ported banks, and to spread long bursts of conflicting accesses to the same bank over time. Bank address rotation is used to spread long bursts of conflicting accesses over multiple banks. All proposed techniques have been implemented in hardware, and are evaluated for a number of different wireless communication standards. For the 11a|n benchmarks, the overhead of stall cycles resulting from unresolved bank conflicts can be reduced to below 2% with the proposed organization. For 3GPP-LTE, the most demanding wireless standard we evaluated, the overhead is reduced to less than 0.13%. This is achieved with little energy and area overhead, and without any bank-aware compiler support. [ABSTRACT FROM AUTHOR]